Apparatus and method for a hash processing system using multiple hash storage areas
AssigneeCorrent Corporation
InventorSatish N. Anand
Life of this patent
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Abstract
A hash processing system and method for reducing the number of clock cycles required to implement the SHA1 and MD5 hash algorithms by using a common hash memory having multiple storage areas each coupled to one of two or more hash channels. The system further provides implicit padding on-the-fly as data is read from the common hash memory. The system shares register and other circuit resources for MD5 and SHA1 hash circuits that are implemented in each hash channel, and uses pipelined, two-channel SHA1 and pipelined, single-channel MD5 hash architectures to reduce the effective time required to implement the SHA1 and MD5 algorithms.
Claims52
A cryptographic processing system, comprising:
- a cipher circuit to perform encryption processing for a plurality of data packets;
- and
- a hash circuit coupled to receive at least a portion of the plurality of data packets for hash processing after encryption processing by the cipher circuit, wherein the hash circuit comprises:
- (i) a first hash channel and a second hash channel each operable to perform the hash processing using at least two different hash algorithms;
- and
- (ii) a common hash memory coupled to receive the portion of the plurality of data packets, wherein:
- the common hash memory comprises at least a first storage area and a second storage area for storing data, the first and second storage areas each selectively coupled to provide data to the first hash channel or the second hash channel for the hash processing;
- and
- the common hash memory is operable to receive and store data from the cipher circuit into the second storage area while data stored in the first storage area is being hashed.
A hash circuit comprising:
- a common hash memory to receive input data, wherein the common hash memory comprises at least a first storage area and a second storage area;
- a first hash channel to perform hash processing and coupled to receive the input data from the first or second storage areas for hash processing;
- and
- a second hash channel to perform hash processing and coupled to receive the input data from the first or second storage areas for hash processing,
- wherein the first bash channel comprises:
- a first adder to implement a first hash algorithm;
- a second adder to implement a second hash algorithm;
- and
- a padding circuit coupled between the common hash memory, the first adder, and the second adder operable to selectively add padding to portions of the input data received from the common hash memory prior to providing to the first second adders.
A hash circuit comprising:
- a common hash memory to receive input data, wherein the common hash memory comprises at least a first storage area, a second storage area, and a third storage area;
- a hash channel to perform hash processing and coupled to selectively receive the input data from the first or second storage areas for hash processing;
- and
- wherein:
- the common hash memory is operable to receive and store additional input data in the second storage area while data stored in the first storage area is being hashed by the hash channel;
- the common hash memory is operable to selectively receive the input data in a repeating sequential order into the first, second, and third storage areas;
- and
- the hash circuit selectively provides the input data received in one of the first, second, or third storage areas to the hash channel to beam hash processing when the storage area is full or an end-of-packet state exists for the input data.
Dependencies are inferred from the claim text.