Common feature mode for microprocessors in a multiple microprocessor system
AssigneeMicrosoft Corporation
InventorsValerie R. See, David W. Williams
Life of this patent
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AssigneeMicrosoft Corporation
InventorsValerie R. See, David W. Williams
Estimating the term…
A mechanism whereby a set of microprocessors may be set to a common mode in which the microprocessors utilize one or more features that are common to all microprocessors. The common mode facilitates proper multiprocessor operation and permits a fix (e.g., a microcode patch) to be applied to each of the microprocessors based on this common mode. More particularly, at system startup, firmware or software can detect whether microprocessors are set to run in different modes (e.g., steppings) in a multiprocessor system. If not, the microprocessors are allowed to run in their normal mode, such as by writing a particular value (e.g., zero) to a configuration register associated with each microprocessor. If features are mixed, a different value can be written, (e.g., one), which tells each microprocessor to revert to a common mode of operation for that family of microprocessors, such as corresponding to a common stepping and/or clock speed. A common set of microcode patches may be downloaded to the microprocessors. Alternatively, the various microprocessors may also be instructed to run in a particular mode that emulates a particular stepping, e.g., by writing into the configuration register or registers a number between one and M that corresponds to a common stepping among the microprocessors.
In a computing environment including a plurality of computing elements and an intermediary mechanism, each computing element including internal components configured for operation in one or more different operating modes, a method for adjusting an operating mode to improve interoperability between the computing elements, the method comprising:
In a computing environment, a system comprising:
In a computing environment including plurality of computing elements and an intermediary mechanism, each computing element including internal components configured for operation in one or more different operating modes, a method for adjusting the operating modes of the plurality of computing elements to improve interoperability between the computing elements, the method comprising:
Dependencies are inferred from the claim text.