Globally observing load operations prior to fence instruction and post-serialization modes
AssigneeIntel Corporation
InventorsLance E. Hacking, Debbie Marr
Life of this patent
Estimating the term…
Abstract
A system includes a memory unit and a processor where the processor has a load buffer to store a first instruction and a cache controller to block the first instruction from dispatch into the cache controller until load data for load operations prior to the first instruction fetched from the memory unit are globally observed. The processor further may include a control register having a first mode storage to store a mode control selection for pre-serialization and a second mode storage to store a mode control selection for post-serialization to enable control of pre-serialization and post-serialization of load operations with respect to the first instruction. Other embodiments are described and claimed.
Claims17
A system comprising:
- a memory unit;
- a processor, the processor comprising a load buffer to store a first instruction and a cache controller to block the first instruction from dispatch into the cache controller until load data for load operations prior to the first instruction fetched from the memory unit are globally observed, the processor further including a control register to enable control of pre-serialization and post-serialization of load operations with respect to the first instruction, the control register having a first mode storage to store a mode control selection for the pre-serialization and a second mode storage to store a mode control selection for the post-serialization;
- a memory controller;
- a bus to couple the memory unit and the memory controller to the processor.
A system comprising:
- a memory unit;
- a processor coupled to the memory unit, the processor including a buffer to store pending instructions including a fence instruction, and a cache controller to block the fence instruction from dispatch into the cache controller until load operations associated with any of the pending instructions prior to the fence instruction are globally observed, the processor further including a control register including a post-serialization control indicator to enable selection of a first mode or a second mode for post-serialization of instructions occurring subsequent to the fence instruction, wherein the first mode is to allow at least some instructions subsequent to the fence instruction to execute out of order with respect to the fence instruction and the second mode is to prevent the instructions subsequent to the fence instruction from execution out of order with respect to the fence instruction;
- a memory controller;
- a bus to couple the memory unit and the memory controller to the processor.
Dependencies are inferred from the claim text.