Using run-time generated instructions in processors supporting wider immediate addressing than register addressing
AssigneeAltera Corporation
InventorAndrew Hall
Life of this patent
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Abstract
The processor typically uses address registers having a particular bit width to access lines within an address space. The bit width limits the address space to a particular size. Techniques are provided for expanding the allowed address bit width and the corresponding address space size by using immediate addressing. Mechanisms allow the run time generation of instructions that can access an array of addresses of varying size, providing a way of implementing address spaces that are not limited by the bit width of address registers.
Claims26
A programmable chip, comprising:
- a processor core;
- a plurality of address registers having a first bit width, the address registers being associated with the processor core on the programmable chip;
- and
- memory coupled to the processor core, the memory configurable to have an address space using a second bit width greater than the first bit width;
- an instruction format supported by the processor core that includes an address of a memory location having said second bit width, wherein the processor core is operable to use immediate addressing to access memory addresses having the second bit width upon generating an instruction during run time that uses said instruction format.
A method for accessing memory by a processor core, the method comprising:
- allocating space in memory that can be accessed by both program buses and data buses of the processor core;
- generating an instruction in the allocated space during run time, wherein the instruction includes an address of a memory location to be used for immediate addressing;
- executing the instruction using immediate addressing;
- determining whether the instruction is a read instruction or a write instruction;
- and
- returning data extracted by the instruction when the instruction is determined to be a read instruction.
A programmable chip, comprising:
- a processor core;
- a plurality of address registers having a first bit width, the address registers being associated with the processor core on the programmable chip;
- and
- memory coupled to the processor core, the memory configurable to have an address space using a second bit width greater than the first bit width;
- an instruction format supported by the processor core that includes an address of a memory location having said second bit width, wherein the processor core includes means for accessing memory addresses having the second bit width with an instruction generated during run time that uses said instruction format.
Dependencies are inferred from the claim text.