Method and system for controlling memory accesses to memory modules having a memory hub architecture

A memory system comprising:

• a plurality of memory modules, each of the memory modules comprising:
• a plurality of memory devices;
• a memory request queue storing at least memory one request received through an input port, the memory request queue being coupled to the memory devices to transmit each memory request stored in the memory request queue to the memory devices, the memory request queue being operable to output a respective read released signal identifying each read memory request transmitted to the memory devices and to output a respective write released signal identifying each write memory request transmitted to the memory devices;
• a flow control unit coupled to the memory request queue, the flow control unit being operable to receive the read released signal and the write released signal from the memory request queue, the flow control unit being operable to output read status signals corresponding to the read released signals and write status signals corresponding to the write released signals;
• a memory read queue coupled to the memory devices, the memory read queue receiving read data from the memory devices and storing the read data for coupling to an output port;
• and
• a response generator coupled to the flow control unit and the memory read queue, the response generator being operable to generate and transmit from an output port read responses each containing the read data from the read data queue and a corresponding one of the read status signals from the flow control unit, the response generator further being operable to transmit from the output port write responses each containing one of the write status signals from the flow control unit;
• and
• a memory hub controller comprising:
• a memory request queue storing at least one memory request received through an input port, the memory request queue being coupled to the memory request queue of each of the memory modules to transmit each memory request stored in the memory request queue to at least one of the memory modules responsive to a flow control signal;
• a response queue coupled to the response generator in each of the memory modules, the response queue being coupled to receive the read responses and the write responses from the response generators in the memory modules, the response queue being operable to couple at least the read data from each of the read responses to a data output port and to couple the read status signal from each read response and the write status signal from each write response to a flow control port;
• and
• a flow control unit coupled to receive the read status signals and the write status signals from the response queue of the memory hub controller, the flow control unit being operable to determine from the status signals the number of outstanding memory requests in each of the memory modules and to generate and couple to the memory request queue of the memory hub controller a flow control signal indicating that additional memory requests can be sent to each of the memory modules based on the number of outstanding memory requests in each of the memory modules.

A processor-based system, comprising:

• a central processing unit (“CPU”);
• a system controller coupled to the CPU, the system controller having an input port and an output port;
• an input device coupled to the CPU through the system controller;
• an output device coupled to the CPU through the system controller;
• a storage device coupled to the CPU through the system controller;
• a memory hub controller storing a plurality of memory requests and outputting each stored memory request responsive to a flow control signal generated as a function of received memory request status signals, the memory hub controller further receiving and storing read data and the memory request status signals, the memory hub controller outputting the stored read data;
• and
• a plurality of memory modules coupled to the memory hub controller, each of the memory modules comprising:
• a plurality of memory devices;
• and
• a memory hub coupled to receive memory requests from the memory hub controller, the memory hub storing the memory requests received from the memory hub controller and coupling memory request signals corresponding to the stored memory requests to the memory devices in the memory module, the memory hub being operable to receive read data from the memory devices and to couple the read data to the memory hub controller, the memory hub further being operable to couple to the memory hub controller the memory request status signals, the memory request status signals identifying the memory requests that have been serviced by the memory devices coupled to the memory hub.

A processor-based system, comprising:

• a central processing unit (“CPU”);
• a system controller coupled to the CPU, the system controller having an input port and an output port;
• an input device coupled to the CPU through the system controller;
• an output device coupled to the CPU through the system controller;
• a storage device coupled to the CPU through the system controller;
• a plurality of memory modules, each of the memory modules comprising:
• a plurality of memory devices;
• a memory request queue storing at least memory one request received through an input port, the memory request queue being coupled to the memory devices to transmit each memory request stored in the memory request queue to the memory devices, the memory request queue being operable to output a respective read released signal identifying a read memory request transmitted to the memory devices and to output a respective write released signal identifying a write memory request transmitted to the memory devices;
• a flow control unit coupled to the memory request queue, the flow control unit being operable to receive the read released signal and the write released signal from the memory request queue, the flow control unit being operable to output read status signals corresponding to the read released signals and write status signals corresponding to the write released signals;
• a memory read queue coupled to the memory devices, the memory read queue receiving read data from the memory devices and storing the read data for coupling to an output port;
• and
• a response generator coupled to the flow control unit and the memory read queue, the response generator being operable to generate and transmit from an output port read responses each containing the read data from the read data queue and a read status signal corresponding to one of the read status signals from the flow control unit, the response generator further being operable to transmit from the output port write responses each containing a write status signal corresponding to one of the write status signals from the flow control unit;
• and
• a memory hub controller comprising:
• a memory request queue storing at least one memory request received through an input port, the memory request queue being coupled to the memory request queue of each of the memory modules to transmit each memory request stored in the memory request queue to at least one of the memory modules responsive to a flow control signal;
• a response queue coupled to the response generator in each of the memory modules, the response queue being coupled to receive the read responses and the write responses from the response generators in the memory modules, the response queue being operable to couple at least the read data from each read response to a data output port and to couple the read status signal from each read response and the write status signal from each write response to a flow control port;
• and
• a flow control unit coupled to receive the read status signals and the write status signals from the response queue of the memory hub controller, the flow control unit being operable to determine from the status signals the number of outstanding memory requests in each of the memory modules and to generate and couple to the memory request queue of the memory hub controller a flow control signal indicating that additional memory requests can be sent to each of the memory modules based on the number of outstanding memory requests in each of the memory modules.

A method of reading data from and writing to a plurality of memory modules, comprising:

• transmitting a plurality of memory request to the memory modules;
• receiving each of the transmitted memory requests at the memory modules;
• servicing the received memory requests in one of the memory modules at a rate that may differ from the rate at which the memory requests are transmitted to the memory module;
• determining the number of memory requests that have been transmitted to the memory modules but not yet serviced by one of the memory modules;
• and
• transmitting additional memory request to the memory modules as a function of the determination made as to the number of transmitted memory requests that have not yet been serviced by the memory module.

In a computer system having a memory hub controller coupled to a plurality of memory modules each of which includes a plurality of memory devices, a method of accessing the memory modules using the memory hub controller, comprising:

• transmitting a plurality of memory request from the memory hub controller to at least one of the memory modules;
• storing the transmitted memory requests in the memory module to which the memory requests are transmitted;
• accessing the memory devices in the memory module in accordance with the memory requests, the memory devices being accessed at a rate that may differ from the rate at which the memory requests are transmitted to the memory modules;
• generating in each of the memory modules memory request status signals that identify which memory requests have been serviced in the memory module;
• coupling the memory request status signals to the memory hub controller;
• and
• transmitting additional memory requests from the memory hub controller to the memory modules as a function of the memory request status signals coupled to the memory hub controller.