Buffering and interleaving data transfer between a chipset and memory modules

An apparatus, comprising:

• a memory buffer including
• a memory module sub-interface to communicate with a memory module,
• a chipset sub-interface to communicate with a chipset, the chipset sub-interface being electrically isolated from the memory module sub-interface and including outputs to output data in an interleaved mode with data from another memory buffer, and
• a data latch to latch data being transferred between the chipset sub-interface and the memory module sub-interface such that the chipset sub-interface and memory module sub-interface operate independently but in synchronization with each other.

An apparatus comprising:

• a buffer to be disposed in an interface between a chipset and one or more memory modules, the buffer including
• a first sub-interface with one of the chipset and the memory modules,
• a second sub-interface with the other of the chipset and the memory modules, the second sub-interface operated at a different voltage level and at a lower frequency than the first sub-interface, and
• control logic to coordinate an output of data from the buffer in an interleaved mode with data from another buffer.