US 7,249,207 B2Granted

Internal data bus interconnection mechanism utilizing central interconnection module converting data in different alignment domains

AssigneeInternational Business Machines Corporation

InventorsMark Anthony Check, Bernard Charles Drerup, Michael Grassi

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Abstract

An integrated circuit chip includes multiple functional components and a central interconnect (CI) module. Each functional component communicates with the CI module via a respective internal bus sharing a common architecture which does not dictate any particular data alignment. The chip architecture defines an alignment mechanism within the CI module, which performs any required alignment of transmitted data. Alignment mechanism design parameters can be varied to accommodate different alignment domains of different functional components. Preferably, the common bus architecture supports multiple internal bus widths, the CI module performing any required bus width conversion. Preferably, for certain transactions not containing a data address, correct alignment is obtained by placing restrictions on transaction size and boundaries, and duplicating certain data on different alignment boundaries. The use of a common bus protocol and CI module having alignment capability streamlines the design process and reduces the overhead of alignment conversion.

Claims18

Dependent claims

An integrated circuit chip for a digital data device, comprising:

a plurality of functional component modules;
a central interconnect module;
a respective communications bus corresponding to each of said plurality of functional component modules, each respective communications bus connecting the corresponding functional component module with said central interconnect module, each respective communications bus employing a common architectural protocol which does not dictate a data alignment, said communications buses and said central interconnect module forming a plurality of communications paths between respective different pairs of said plurality of functional component modules, each of said plurality of communications paths comprising a communications bus corresponding to a first functional component module of a respective one of said pairs of said plurality of functional component modules, said central interconnect module, and a communications bus corresponding to a second functional component module of the respective pair of functional component modules;
wherein a respective data alignment boundary corresponds to each said functional component module, wherein data sent and received by each functional component module on a communications bus corresponding to the respective functional component module is aligned on the data alignment boundary corresponding to the respective functional component module;
wherein, for at least one misaligned pair of said plurality of pairs of functional component modules, the alignment boundary corresponding to a first functional component module of the misaligned pair is different from the alignment boundary corresponding to a second functional component module of the misaligned pair;
and
wherein said central interconnect module includes data alignment logic aligning each data transmission traversing the central interconnect module along a communications path of said plurality of communications paths along a respective alignment boundary corresponding to the functional component module receiving the data transmission.

4 more elements

A method of designing an integrated circuit chip, comprising the steps of:

defining a plurality of functional component modules, each functional module being associated with a respective data alignment boundary;
incorporating a pre-existing definition of a central interconnect module, said central interconnect module definition providing a plurality of ports for connection to respective communications buses employing a common protocol and internal connections between at least some of said ports, said central interconnect module definition further defining data alignment logic for aligning data transmissions being transmitted between respective pairs of said functional component modules by said central interconnect module;
and
defining a plurality of communications buses employing said common architectural protocol, each bus of said plurality of communications buses being connected between a respective one of said functional component modules and a respective port of said plurality of ports of said central interconnect module, each communications bus transmitting data according to the data alignment boundary associated with the respective functional component module, said plurality of communications buses and said central interconnect module forming a plurality of communications paths between respective different pairs of said plurality of functional component modules, each of said plurality of communications paths comprising a communications bus corresponding to a first functional component module of a respective one of said pairs of said plurality of functional component modules, said central interconnect module, and a communications bus corresponding to a second functional component module of the respective pair of functional component modules, wherein, for at least one misaligned pair of said plurality of pairs of functional component modules, the alignment boundary corresponding to the first functional component module of the misaligned pair is different from the alignment boundary corresponding to the second functional component module of the misaligned pair;
and
specifying at least one alignment conversion to be performed by said data alignment logic.

3 more elements

Dependencies are inferred from the claim text.