System for generating pseudorandom sequences
AssigneeInterDigital Technology Corporation
InventorEdward L. Hepler
Life of this patent
Estimating the term…
Abstract
A system for generating pseudorandom codes using a register which contains an identification of the code tree leg of the desired code and a counter which outputs a successive binary sequence. The output from the counter is bit-by-bit ANDed with the output of the register, and those outputs are XORed together to output a single bit. As the counter is sequenced, each count results in a different bit that is output from the XOR gate, resulting in the desired code.
Claims5
A system for generating an OVSF code comprising:
- a binary counter for providing a binary count comprising a plurality of sequential M-bit binary numbers, each binary number being ordered from most significant bit to least significant bit;
- bit reordering means, for selectively reordering the bits of each said binary number from least significant bit to most significant bit;
- an index selector, for providing an M-bit binary identification of said OVSF code;
- and
- a logical reduction means having a first input from the reordering means and a second input from the index selector and having an output;
- whereby the desired OVSF code is output from said output.
A code generator for generating individual binary codes of a set of binary codes, each binary code having 2M bits, the code generator comprising:
- a counter having an output and sequentially outputting M-bit counts in a parallel orientation, each successive count being incremented by 1;
- bit reordering means, coupled to said output of said counter, for receiving each M-bit count, whereby the M-bit counts are ordered from least significant bit to most significant bit, and whereby said bit reordering means reorders the bits from most significant bit to least significant bit;
- an index selector for outputting an M-bit code identifier in a parallel orientation;
- a parallel array of M logical gates, each having an output and a first input being one parallel bit from said bit ordering means and a second input being one parallel bit from said index selector;
- and
- a reduction network of logical gates associated with the outputs of said parallel array of logical gates for outputting a single code bit each time a parallel M-bit count is input to said parallel logical gate array from said bit ordering means, such that the binary code which is identified by the M-bit code identifier is produced after 2M iterations.
A system for generating a desired pseudorandom code comprising:
- a binary counter for providing a plurality of M-bit sequential binary numbers, each binary number being ordered from most significant bit to least significant bit;
- bit reordering means for reordering the bits of said binary counter from least significant bit to most significant bit;
- an index selector, for outputting an M-bit code identifier of the desired pseudorandom code;
- at least M logical gates, each having a first input from said bit ordering means and a second input from said index selector, and each having an output;
- and
- an XOR tree for XORing said outputs of said logical gates to provide an XORed output;
- whereby the desired pseudorandom code is output from said XORed output.
A code generator for generating an individual binary code from a set of N binary codes, each binary code having M bits, the code generator comprising:
- a counter having an output and sequentially outputting M-bit binary numbers, each successive binary number being incremented by 1;
- bit reordering means, coupled to said output of said counter, for receiving each M-bit binary number having bits ordered from least significant bit to most significant bit, whereby said bit reordering means reorders the bits from most significant bit to least significant bit;
- an index selector for outputting an M-bit code;
- a logical gate array having a first input from said bit reordering means and a second input from said index selector, and having an output;
- a reduction network of logical gates associated with said output of said logical gate array for outputting a single code bit each time an M-bit binary number is input to said logical gate array from said bit ordering means, such that the binary code identified by the M-bit code is produced after 2M iterations.
Dependencies are inferred from the claim text.