US 7,248,663 B2Granted

Apparatus and method for transforming data transmission speed

AssigneeLG-Nortel Co., Ltd.

InventorYun-Jun Jeong

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Abstract

Disclosed is an apparatus and method for transforming data transmission speed that transforms data transmission speeds of data transmitting apparatuses that have different data transmission speeds using a DPRAM. By using a DPRAM to transform transmission speeds, the apparatus and method for transforming data transmission speed is simplified, thereby improving the procedure for transforming data transmission speed. Furthermore, it is possible to prevent data from being lost at the time of transforming data transmission speed.

Claims20

Dependent claims

An apparatus for transforming data transmission speed, comprising:

a transmission speed transforming circuit that receives data of a first transmission speed, through a first frame synchronizing signal of a first data bus of the first transmission speed, by synchronizing a first clock with a first reference clock of the first data bus;
and
a Dual Port Random Access Memory (DPRAM) coupled to receive and store the data from the transmission speed transforming circuit, wherein the transmission speed transforming circuit to read the stored data from the DPRAM and transmit the data with a second transmission speed, through a second frame synchronizing signal of a second data bus of the second transmission speed, by synchronizing a second clock with a second reference clock of the second data bus, wherein the transmission speed transforming circuit comprises:
a data reception circuit that receives data of the first transmission speed through the first frame synchronizing signal by synchronizing the first clock of that data reception circuit with the first reference clock;
a data transmission circuit that transmits data of the second transmission speed through the second frame synchronizing signal by synchronizing the second clock of the data transmission circuit with the second reference clock;
an address control circuit that generates a control signal in order to write the data of the first transmission speed in the DPRAM and read the data of the second transmission speed from the DPRAM;
a reception address generation circuit that generates addresses for writing the data of the first transmission speed in the DPRAM according to the control signal of the address control circuit;
a reception data generation circuit that transforms the data of the first transmission speed into data to be written in the DPRAM;
a transmission address generation circuit that generates addresses for reading the data of the second transmission speed from the DPRAM according to the control signal of the address control circuit;
and
a transmission data generation circuit that transforms the data of the second transmission speed into data to be transmitted by the data transmission circuit.

8 more elements

An apparatus for transforming data transmission speed, comprising:

a transmission speed transforming circuit that receives and stores data of a first transmission speed, through a first frame synchronizing signal of a first data bus, by synchronizing a clock with a first reference clock of the first data bus, and reads and transmits data of a second transmission speed, through a second frame synchronizing signal of a second data bus, by synchronizing the clock with a second reference clock of the second data bus;
and
a Dual Port Random Access Memory coupled to receive and store the data of the first transmission speed according to the control of the transmission speed transforming circuit, and further to output the data of the second transmission speed according to the control of the transmission speed transforming circuit, wherein the transmission speed transforming circuit comprises:
a data reception circuit that receives data of the first transmission speed through the first frame synchronizing signal by synchronizing the clock with the first reference clock;
a data transmission circuit that transmits data of the second transmission speed through the second frame synchronizing signal by synchronizing the clock with the second reference clock;
an address control circuit that generates a control signal in order to write the data of the first transmission speed in the DPRAM and read the data of the second transmission speed from the DPRAM;
a reception address generation circuit that generates addresses for writing the data of the first transmission speed in the DPRAM according to the control signal of the address control circuit;
a reception data generation circuit that transforms the data of the first transmission speed into data to be written in the DPRAM;
a transmission address generation circuit that generates addresses for reading the data of the second transmission speed from the DPRAM according to the control signal of the address control circuit;
and
a transmission data generation circuit that transforms the data of the second transmission speed into data to be transmitted by the data transmission circuit.

8 more elements

An apparatus for transforming data transmission speed comprising:

a data reception circuit of a first transmission speed that receives data of the first transmission speed through a first frame synchronizing signal of a first data bus by synchronizing a clock with a first reference clock;
a data transmission circuit that transmits data of a second transmission speed through a second frame synchronizing signal of a second data bus by synchronizing the clock with a second reference clock;
a Dual Port Random Access Memory (DPRAM) that stores the data of the first transmission speed and the data of the second transmission speed;
an address control circuit that generates a control signal in order to write the data of the first transmission speed in the DPRAM and read the data of the second transmission speed from the DPRAM;
a reception address generation circuit that generates addresses for writing the data of the first transmission speed in the DPRAM according to the control signal of the address control circuit;
a reception data generation circuit that transforms the data of the first transmission speed into data to be written in the DPRAM;
a transmission address generation circuit that generates addresses for reading the data of the second transmission speed from the DPRAM according to the control signal of the address control circuit;
and
a transmission data generation circuit that transforms the data of the second transmission speed into data to be transmitted by the data transmission circuit.

6 more elements

Dependencies are inferred from the claim text.

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Abstract

An apparatus for transforming data transmission speed, comprising:

a transmission speed transforming circuit that receives data of a first transmission speed, through a first frame synchronizing signal of a first data bus of the first transmission speed, by synchronizing a first clock with a first reference clock of the first data bus;
and
a Dual Port Random Access Memory (DPRAM) coupled to receive and store the data from the transmission speed transforming circuit, wherein the transmission speed transforming circuit to read the stored data from the DPRAM and transmit the data with a second transmission speed, through a second frame synchronizing signal of a second data bus of the second transmission speed, by synchronizing a second clock with a second reference clock of the second data bus, wherein the transmission speed transforming circuit comprises:
a data reception circuit that receives data of the first transmission speed through the first frame synchronizing signal by synchronizing the first clock of that data reception circuit with the first reference clock;
a data transmission circuit that transmits data of the second transmission speed through the second frame synchronizing signal by synchronizing the second clock of the data transmission circuit with the second reference clock;
an address control circuit that generates a control signal in order to write the data of the first transmission speed in the DPRAM and read the data of the second transmission speed from the DPRAM;
a reception address generation circuit that generates addresses for writing the data of the first transmission speed in the DPRAM according to the control signal of the address control circuit;
a reception data generation circuit that transforms the data of the first transmission speed into data to be written in the DPRAM;
a transmission address generation circuit that generates addresses for reading the data of the second transmission speed from the DPRAM according to the control signal of the address control circuit;
and
a transmission data generation circuit that transforms the data of the second transmission speed into data to be transmitted by the data transmission circuit.

8 more elements