US 7,248,661 B1 · Data transfer between phase independent clock domains

Abstract

An integrated circuit arrangement clocked by a single clock having variable delays to different regions of said arrangement such that said regions are partially synchronized to each other, the arrangement comprising: a data transfer buffer for buffering a data stream for transfer between respective first and second ones of said regions, and a data transfer controller, associated with said data transfer buffer and said respective regions, configured to control transfer of said data stream by: initially synchronizing between said respective regions at a start of said data stream, receiving data, in said buffer, from said first region, at a predetermined rate, and outputting said data stream to said second region at said predetermined rate in accordance with said initial synchronization. The arrangement allows deterministic data patterns to arrive at the receiving domain at minimal hardware cost.

Claims28

Dependent claims

A method of transferring a multi-word data stream between a first electronic component region and a second electronic component region, said multi-word data stream having a start and a continuation, said component regions being clocked such as to have a frequency ratio therebetween variable about an average value, and a maximum mutual jitter between the two clocks the method comprising:

outputting said start from said first component region,
outputting a synchronization signal to indicate timing of outputting of said start,
outputting said continuation from said first electronic component region at a first predetermined rate,
buffering said data stream including said start and said continuation,
using said synchronization signal to establish an initial synchronization with said second electronic component region,
outputting said buffered start of said data stream to said second electronic component region in accordance with said initial synchronization, and
outputting said continuation to said second electronic component region at substantially said first predetermined rate, at timings dictated by said initial synchronization.

4 more elements

An arrangement comprising at least one integrated circuit, said arrangement being clocked by at least one signal obtained from a single clock having variable delays to different regions of said arrangement such that said regions are partially synchronized to each other, having a mutual clock frequency ratio therebetween which varies about an average value and a maximum mutual clock jitter, the arrangement comprising:

a data transfer buffer for buffering parts of multi-word data streams during transfer between respective first and second ones of said regions, and
data transfer control functionality, associated with said data transfer buffer and said respective regions, configured to control transfer of said data stream, said functionality comprising:
synchronizing logic for detecting at least a start of transfer of said multi-word data stream, issuing a synchronizing signal based on timing at said first region, and using said synchronizing signal to form an initial synchronization with said second region, and
rate control logic for receiving data of said multi-word data stream, in said buffer, from said first region, at a predetermined rate,
said data transfer control functionality being operable to withhold forwarding of said data stream from said buffer to said second region by at least a synchronizing delay indicated by said initial synchronization, said rate control logic further being configured to carry out said forwarding to said second region at substantially said predetermined rate.

2 more elements

Dependencies are inferred from the claim text.

Data transfer between phase independent clock domains

Life of this patent

Data transfer between phase independent clock domains

Life of this patent

Abstract

Claims28