Method and circuit for deriving a second clock signal from a first clock signal
AssigneeNEC Corporation
InventorFilip Zalio
Life of this patent
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Abstract
A clock generation circuit for a dual system radio frequency station is provided. The station includes a digital synthesis circuit clocked by a first clock signal for a first RF system that is adapted to generate a base signal output of a predetermined frequency. A second clock signal is derived from the sum of the frequency of the base signal and the frequency of the first clock signal.
Claims6
A clock generation circuit for a dual communications technology system radio frequency (RF) station, including:
- a digital clock synthesis circuit clocked by a first clock signal for a first communications technology RF system and adapted to generate an analog base clock signal of a predetermined frequency;
- and
- means for deriving a second clock signal for a second communications technology RF system from an output of said digital clock synthesis circuit as a Nyquist image derived from said first clock signal.
A clock generation circuit for a dual communications technology system radio frequency (RF) station, including:
- a digital clock synthesis circuit clocked by a first clock signal for a first communications technology RF system and adapted to generate an analog base clock signal of a predetermined frequency;
- and
- means for deriving a Nyquist image derived from said first clock signal, said Nyquist image having the frequency of a second clack signal for a second communications technology RF system.
A method for deriving a second clock signal for a second communications technology system from a first clock signal of a first communications technology system, where a frequency of said second clock signal is greater than half of a frequency of said first clock signal, including:
- clocking a direct digital clock synthesis circuit with said first clock signal of a first communications technology system to generate an analog base clock signal;
- applying a phase step in said synthesis circuit such that a sum of a frequency of said analog base clock signal and the frequency of said first clock signal has the frequency of said second clock signal for a second communications technology system;
- and
- deriving said second clock signal from an output of said digital clock synthesis circuit.
Dependencies are inferred from the claim text.