Method and apparatus for communicating computer data from one point to another over a communications medium

A communication channel comprising:

• a link level protocol having an input/output, a driver line and a receiver line;
• a driver connected to the driver line, wherein the driver includes a driver output;
• a canceller/equalizer connected to the driver line and the driver output, wherein the canceller/equalizer includes a canceller/equalizer output, and wherein the canceller/equalizer generates a receive signal as a function of data on the driver line and the driver output;
• and
• a receiver connected to the receiver line and the canceller/equalizer output, wherein the receiver includes a receiver circuit and a bit deskew circuit, wherein the bit deskew circuit deskews signals from the receiver circuit as a function of a clock signal.

A communication channel comprising:

• a link level protocol having an input/output, a driver line and a receiver line;
• a driver connected to the driver line, wherein the driver includes a driver output, a driver circuit, and an impedance control circuit, wherein the impedance control circuit includes an impedance control output connected to the driver circuit, and wherein the impedance control circuit modifies a driver output signal as a function of an external signal;
• a canceller/equalizer connected to the driver line and the driver output, wherein the canceller/equalizer includes a canceller/equalizer output, and wherein the canceller/equalizer generates a receive signal as a function of data on the driver line and the driver output;
• and
• a receiver connected to the receiver line and the canceller/equalizer output, wherein the receiver includes a receiver circuit and a bit deskew circuit, wherein the bit deskew circuit deskews signals from the receiver circuit as a function of a clock signal.

A communications system, comprising:

• a communications medium;
• a plurality of processors including a first and second processor, wherein each processor includes at least one processor line;
• a first transceiver connected to the first processor and to the communications medium, wherein the first transceiver comprises a link level protocol, a driver including a driver output, a driver circuit and an impedance control circuit, a canceller/equalizer, and a receiver;
• and
• a second transceiver connected to the second processor and to the communications medium, wherein the second processor communicates with the first processor over the communications medium;
• wherein the link level protocol includes an input/output, a driver line and a receiver line;
• wherein the driver is connected to the driver line, wherein the impedance control circuit includes an impedance control output connected to the driver circuit, and wherein the impedance control circuit modifies a driver output signal as a function of an external signal;
• wherein the canceller/equalizer is connected to the driver line and the driver output, wherein the canceller/equalizer includes a canceller/equalizer output, and wherein the canceller/equalizer generates a receive signal as a function of data on the driver line and the driver output;
• and
• wherein the receiver is connected to the receiver line and the canceller/equalizer output.

A communications system comprising:

• a communications medium;
• a plurality of processors including a first and second processor, wherein each processor includes at least one processor line;
• a first transceiver connected to the first processor and to the communications medium, wherein the first transceiver comprises a link level protocol, a driver including a driver output, a driver circuit and an impedance control circuit, a canceller/equalizer, and a receiver including a receiver circuit and a bit deskew circuit;
• and
• a second transceiver connected to the second processor and to the communications medium, wherein the second processor communicates with the first processor over the communications medium;
• wherein the link level protocol includes an input/output, a driver line and a receiver line;
• wherein the driver is connected to the driver line, wherein the impedance control circuit includes an impedance control output connected to the driver circuit, and wherein the impedance control circuit modifies a driver output signal as a function of an external signal;
• wherein the canceller/equalizer is connected to the driver line and the driver output, wherein the canceller/equalizer includes a canceller/equalizer output, and wherein the canceller/equalizer generates a receive signal as a function of data on the driver line and the driver output;
• and
• wherein the receiver is connected to the receiver line and the canceller/equalizer output, wherein the bit deskew circuit deskews signals from the receiver circuit as a function of a clock signal.

A communications system, comprising:

• a communications medium;
• a processor with at least one processor line;
• and
• a transceiver connected to the processor and to the communications medium, wherein the transceiver comprises a link level protocol, a driver including a driver output, a driver circuit and an impedance control circuit, a canceller/equalizer, and a receiver;
• wherein the link level protocol includes an input/output, a driver line and a receiver line;
• wherein the driver is connected to the driver line, wherein the impedance control circuit includes an impedance control output connected to the driver circuit, and wherein the impedance control circuit modifies a driver output signal as a function of an external signal;
• wherein the canceller/equalizer is connected to the driver line and the driver output, wherein the canceller/equalizer includes a canceller/equalizer output, and wherein the canceller/equalizer generates a receive signal as a function of data on the driver line and the driver output;
• and
• wherein the receiver is connected to the receiver line and the canceller/equalizer output.

A communications system, comprising:

• a communications medium;
• a processor with at least one processor line;
• and
• a transceiver connected to the processor and to the communications medium, wherein the transceiver comprises a link level protocol, a driver including a driver output, a driver circuit and an impedance control circuit, a canceller/equalizer, and a receiver including a receiver circuit and a bit deskew circuit;
• wherein the link level protocol includes an input/output, a driver line and a receiver line;
• wherein the driver is connected to the driver line, wherein the impedance control circuit includes an impedance control output connected to the driver circuit, and wherein the impedance control circuit modifies a driver output signal as a function of an external signal;
• wherein the canceller/equalizer is connected to the driver line and the driver output, wherein the canceller/equalizer includes a canceller/equalizer output, and wherein the canceller/equalizer generates a receive signal as a function of data on the driver line and the driver output;
• and
• wherein the receiver is connected to the receiver line and the canceller/equalizer output, wherein the bit deskew circuit deskews signals from the receiver circuit as a function of a clock signal.