Efficient multi-threaded multi-processor scheduling implementation
AssigneeIntel Corporation
InventorsPrashant R Chandra, Alok Kumar
Life of this patent
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Abstract
A system and method of scheduling packets in a multi-threaded, multiprocessor network architecture provides enhanced speed and performance. The architecture involves a scheduler thread that transitions between queues in response to a depletion of queues by a weighted amount, a plurality of transmit threads that deplete the queues by the size of packets transmitted and a plurality of receive threads that initialize the weights for idle queues.
Claims33
A method of processing packets, comprising:
- transferring packets from a plurality of queues of a processor first off-chip memory to a transmit buffer with execution of a first transmit thread;
- transferring packets from the plurality of queues to the transmit buffer with execution of a second transmit thread, the transmit threads to transition between the queues in response to a depletion of each queue by a weighted amount;
- and
- using a scheduler threat to select a first queue based on the queues with credit (QWC) vector.
A method of processing packets, comprising:
- using a schedule thread to select a first queue from a plurality of queues based on a queues with credit (QWC) vector;
- transferring a first packet from the first queue to a transmit buffer;
- reducing a credit descriptor of the first queue by an amount corresponding to a size of the first packet;
- determining whether the reducing causes the credit descriptor of the first queue to be depleted by a first weighted amount;
- updating the QWC vector based on the determining;
- and transferring a second packet from a second queue to the transmit buffer if the reducing causes the credit descriptor of the first queue to be depleted by the first weighted amount.
A processor comprising:
- a transmit buffer;
- a plurality of transmit threads to transfer packets from a plurality of queues of a first off-chip memory to the transmit buffer, the transmit threads to transition between the queues in response to a depletion of the queues by weighted amounts;
- and
- an on-chip memory to queues with packets (QWP) vector and a queues with credit (QWC) vector, each vector having a plurality of bits corresponding to the plurality of queues.
A networking architecture comprising:
- a first off-chip memory having a plurality of queues;
- a second off-chip memory to store a credit descriptor and a weight descriptor for each queue, the weight descriptors to define weighted amounts and the credit descriptors to indicate whether the queues have been depleted by the weighted amounts;
- and
- a processor operatively coupled to the first off-chip memory and the second off-chip memory, the processor including a transmit buffer and a plurality of transmit threads to transmit packets from the queues to the transmit buffer, the transmit threads to transition between the queues in response to a depletion of the queues by the weighted amounts, the processor further includes an on-chip memory to store a queues with packets (QWP) vector and a queues with credit (QWC) vector, each vector having a plurality of bits corresponding to the plurality of queues.
A computer readable medium storing a set of instructions to be executed by a processor to:
- transfer packets from a plurality of queues of a processor first off-chip memory to a transmit buffer using a first transmit thread;
- and
- transfer packets from the plurality of queues to the transmit buffer using a second transmit thread, the transmit threads to transition between the queues in response to depletion of each queue by a weighted amount, the instructions are to be executed to use a scheduler thread to select a first queue based on a queues with credit (QWC) vector.
Dependencies are inferred from the claim text.