Partitionable data fabric and computing arrangement
AssigneeHewlett-Packard Development Company, L.P.
InventorGregory S. Snider
Life of this patent
Estimating the term…
Abstract
A circuit arrangement and method for interfacing a node and a data fabric. In a computing arrangement that includes a plurality of nodes intercoupled by the data fabric, each node is assigned to one of a plurality of partitions. A node-interface circuit is configured to interface with the source node, and a translation circuit translates data between a first format compatible with the nodes and a second format compatible with the data fabric. An access control circuit either enables or disables transmission of data from the source node based on whether the source and destination nodes are in the same partition.
Claims8
A circuit arrangement for interfacing a node and a data fabric in a computing arrangement that includes a plurality of nodes intercoupled by the data fabric, wherein each node is assigned to one of a plurality of partitions, and the node from which data are sent is a source node and the node to which data are sent is a destination node, comprising:
- a node-interface circuit configured to interface with the source node;
- a translation circuit coupled to the node-interface circuit and configured to translate data between a first format compatible with the nodes and a second format compatible with the data fabric;
- an access control circuit coupled to the translation circuit, the access control circuit configured to enable and disable transmission of data from the source node to a destination node in response to partition assignments of the nodes;
- and
- a buffer management circuit coupled to the access control circuit and configured to interface with the data fabric.
A computing arrangement comprising:
- a data fabric;
- a plurality of nodes coupled to the data fabric via respective line cards, wherein each node is assigned to one of a plurality of partitions, and the node from which data are sent is a source node and the node to which data are sent is a destination node, and the line card includes,
- a node-interface circuit configured to interface with the source node;
- a translation circuit coupled to the node-interface circuit and configured to translate data from a first format compatible with the nodes and a second format compatible with the data fabric;
- an access control circuit coupled to the translation circuit, the access control circuit configured to enable and disable transmission of data from the source node to a destination node in response to partition assignments of the nodes;
- and
- a buffer management circuit coupled to the access control circuit and configured to interface with the data fabric.
Dependencies are inferred from the claim text.