Method and apparatus for a packet classifier

A method for performing optimistic hash matching, comprising:

• defining a lookup table having a plurality of values stored therein, each of the plurality of values being associated with at least one processor;
• receiving a packet;
• extracting a key from the packet;
• calculating a first hash value and a second hash value from the key;
• identifying a field of interest within the lookup table corresponding to the first hash value;
• comparing the second hash value to values within the field of interest to identify a match between the second hash value and one of the values within the field of interest;
• and
• sending the received packet to a processor corresponding to the one of the values within the field of interest.

A network interface card, comprising:

• circuitry for receiving a packet;
• packet classifier circuitry, the packet classifier circuitry configured to calculate a first hash value and a second hash value from fields of a packet header of the received packet, the first hash value indicating a field of interest associated with a lookup table in communication with the network interface card, the second hash value matching a value within the field of interest to identify a processor assigned to the packet;
• and
• circuitry for transmitting the packet to a queue associated with the processor assigned to the packet.

A system for efficiently classifying packets in a multicore/multithread environment, comprising:

• a multi-processor chip in communication with a semiconductor chip storing data, the multi-processor chip including,
• a plurality of processor cores;
• a network interface card (NIC) for receiving a packet from a network;
• the NIC having packet classifier circuitry, the packet classifier circuitry configured to calculate a first hash value and a second hash value from a packet header of the packet, the first hash value indicating a field of interest in a table, the second hash value identifying data at a location in the field of interest, the data indicating one of the plurality of processor cores for the packet to be sent to;
• and
• a semiconductor chip configured to store data associated with the table, the semiconductor chip in communication with the multi-processor chip.