Semiconductor memory device

A semiconductor memory device comprising:

• an interface unit that executes transmission/reception of data with an external circuit;
• a data memory unit including a write data line, a read-out data line, a plurality of data control units commonly connected to the interface unit via the write data line, and a plurality of memory blocks each connected to the data control units, respectively;
• and
• a read-out latch block that is connected between the read-out data line and the interface unit,
• wherein the read-out data line is commonly connected to the plurality of data control units, a selected one of the data control units outputs read data, which is read out of a corresponding one of the memory blocks associated with the selected one of the data control units, to the read-out data line with a trailing edge of a clock being used as a trigger, the read-out latch block latches the data with a trailing edge of another clock, which is generated at least one cycle after the trailing edge of the aforementioned clock, being used as a trigger, and the interface unit outputs the data to the external circuit with a leading edge of still another clock, which follows the aforementioned another clock, being used as a trigger.

A semiconductor memory device comprising:

• an interface unit that executes transmission/reception of data with an external circuit;
• a data memory unit including a write data line, a plurality of read-out data lines, a plurality of data control units commonly connected to the interface unit via the write data line, a plurality of memory blocks connected to the plurality of data control units, respectively, and each of the plurality of read-out data lines being connected between a preceding data control unit and a nest data control unit;
• and
• a read-out latch block that is connected between the interface unit and one of the plurality of data control units provided adjacent to the interface unit,
• wherein a selected data control unit of the data control units outputs data, which is read out of a memory block corresponding to the selected data control unit, to the corresponding read-out data line with a trailing edge of a clock being used as a trigger, the read-out latch block latches the data with a trailing edge of another clock, which is generated at least one cycle after the trailing edge of the aforementioned clock, being used as a trigger, and the interface unit outputs the data to the external circuit with a leading edge of still another clock, which follows the aforementioned another clock, being used as a trigger.