US 7,248,536 B2 · Integrated semiconductor memory and method for operating an integrated semiconductor memory

Abstract

A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment (12) of a segmented word line not via a first line (21) otherwise used for deactivation, but rather via a second line (22) via that the word line segment (12) is otherwise activated. The second line (22) can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (12), the word line segment can be driven via a switching element (17), which couples the word line segment to the second line (22), without the complementary switching element (16) of the driver segment (20) having to be used for deactivation. It can thereby be ascertained which of two switching elements (16, 17) of the driver segment is defective and whether or not the semiconductor memory will function in a manner free of errors after permanent replacement of the word line on account of a floating potential of the tested word line segment (12).

Claims25

Dependent claims

An integrated semiconductor memory comprising:

a word line driver that includes a driver segment;
a word line having a master word line and having at least one word line segment, the word line segment being connected to the driver segment of the word line driver and the driver segment being coupled to the master word line;
and
a multiplicity of memory cells, each memory cell having a transistor coupled to a word line;
wherein the word line segment, depending on a bias voltage of the master word line and by means of the driver segment, is electrically connectable either to a first line providing a first potential, which deactivates the word line segment, or to a second line, the second line being able to be biased such that it provides either a second potential, which activates the word line segment, or a third potential, the magnitude of which lies between the first potential and the second potential;
and
wherein, in a first operating mode, in which, upon deactivation of the word line segment, the word line segment is biased with the third potential via the second line, the electrical connection between the word line segment and the first line remains interrupted.

4 more elements

A method for operating an integrated semiconductor memory having at least one word line that includes a master word line and at least one word line segment coupled to a driver segment of a word line driver, the memory further including at least one memory cell having a transistor coupled to the word line segment, wherein, depending on a bias voltage of the master word line, the word line segment is connectable either to a first line providing a first potential or to a second line, the method comprising:

activating the word line segment by coupling the word line segment to the second line and biasing the second line with a second potential that activates the word line segment;
and
deactivating the word line segment by firstly bringing the potential of the second line from the second potential to a third potential, wherein the magnitude of the third potential lies between the first potential and the second potential, and then electrically isolating the word line segment from the second line.

Dependencies are inferred from the claim text.

Integrated semiconductor memory and method for operating an integrated semiconductor memory

Life of this patent

Integrated semiconductor memory and method for operating an integrated semiconductor memory

Life of this patent

Abstract

Claims25