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US 7,248,535 B2Granted
Semiconductor memory devices having negatively biased sub word line scheme and methods of driving the same
AssigneeSamsung Electronics Co., Ltd.
InventorKi-Chul Chun
Life of this patent
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Abstract
Semiconductor memory devices having a negatively biased sub-word line scheme and methods of driving the same are disclosed. In a semiconductor memory device, NMOS transistors for pulling down a word line enable signal and a word line driving signal to a negative voltage are adjusted to a negative voltage. The negatively biased word line scheme may decrease influx of discharge current into the negative voltage source and decrease negative voltage fluctuations and associated noise.
Claims23
A semiconductor memory device, comprising:
- a plurality of sub-word lines;
- a plurality of sub-word line drivers each connected to corresponding sub-word lines, the sub-word line drivers connecting the corresponding sub-word lines to a first voltage in response to corresponding word line enable signals and sub-word line driving signals during a precharge operation;
- a plurality of driving signal generating circuits each connected to a corresponding sub-word line driver and configured to provide the sub-word line driving signals thereto;
- and
- word line enable drivers each connected to a corresponding sub-word line driver and configured to provide the word line enable signals thereto,
- wherein each of the word line enable drivers comprises:
- a decoder input terminal configured to receive an upper decoding signal;
- a decoder control terminal;
- a first decoder pull-down unit configured to pull down the decoder control terminal to a second voltage in response to the upper decoding signal and a predetermined leakage interruption signal;
- a second decoder pull-down unit configured to pull down the decoder control terminal to the first voltage in response to a preliminary signal that is used to generate the word line enable signals;
- a decoder pull-up unit configured to pull up the decoder control terminal in response to the upper decoding signal;
- and
- a driving unit configured to generate the preliminary signal pulled down to the first voltage in response to voltage of the decoder control terminal,
- wherein the leakage interruption signal is adjusted to the first voltage when each word line enable signal is activated.
11 more elements
A semiconductor memory device, comprising:
- a plurality of sub-word lines;
- a plurality of sub-word line drivers each connected to corresponding sub-word lines, the sub-word lines, the sub-word line drivers connecting the corresponding sub-word lines to a first voltage in response to corresponding word line enable signals and sub-word line driving signals during a precharge operation;
- a plurality of driving signal generating circuits each connected to a corresponding sub-word line driver and configured to provide the sub-word line driving signals thereto;
- and
- word line enable drivers each connected to a corresponding sub-word line driver and configured to provide the word line enable signals thereto,
- wherein each of the word line enable drivers comprises:
- a decoder input terminal configured to receive an upper decoding signal;
- a decoder control terminal;
- a first decoder current path formed between the decoder control terminal and the second voltage in response to the upper decoding signal and a leakage interruption signal;
- and
- a second decoder current path formed between the decoder control terminal and the first voltage in response to a preliminary signal that is pulled down to the first voltage in response to voltage of the decoder control terminal,
- wherein the leakage interruption signal is adjusted to the first voltage when each word line enable signal is activated.
9 more elements
A method of driving a semiconductor memory device including at least one sub-word line driver configured to connect a corresponding sub-word line to a first voltage in response to a word line enable signal and a sub-word line driving signal, the method comprising:
- generating by a driving signal generating circuit the sub-word line driving signal and providing the sub-word line driving signal to a corresponding sub-word line driver through a driving output terminal, the driving signal generating circuit having a driving input terminal and the driving output terminal;
- and
- generating by a word line enable driver a pulled down word line enable signal in response to a decoder control terminal and providing the word line enable signal to the corresponding sub-word line driver, the word line enable driver having a decoder input terminal and the decoder control terminal,
- wherein generating by a driving signal generating circuit comprises:
- receiving an upper decoding signal through the decoder input terminal;
- pulling down the decoder control terminal to a second voltage in response to the upper decoding signal and a leakage interruption signal, and pulling down the decoder control terminal to the first voltage in response to a preliminary signal that is used to generate the word line enable signal;
- and
- generating the preliminary signal pulled down to the first voltage in response to voltage of the decoder control terminal,
- wherein the leakage interruption signal is adjusted to the first voltage when the word line enable signal is activated.
6 more elements
A method of driving a semiconductor memory device including at least one sub-word line driver configured to connect a corresponding sub-word line to a first voltage in response to a word line enable signal and a sub-word line driving signal, the method comprising:
- generating by a driving signal generating circuit the sub-word line driving signal and providing the sub-word line driving signal to a corresponding sub-word line driver through a driving output terminal, the driving signal generating circuit having a driving input terminal and the driving output terminal;
- and
- generating by a word line enable driver a pulled down word line enable signal in response to a decoder control terminal and providing the word line enable signal to the corresponding sub-word line driver, the word line enable driver having a decoder input terminal and the decoder control terminal,
- wherein generating by a driving signal generating circuit comprises:
- receiving an upper decoding signal through the decoder input terminal;
- forming a first decoder current path between the decoder control terminal and a second voltage in response to the upper decoding signal and a leakage interruption signal;
- forming a second decoder current path between the decoder control terminal and the first voltage in response to a preliminary signal that is used to generate the word line enable signal;
- and
- pulling down the preliminary signal to the first voltage in response to voltage of the decoder control terminal;
- wherein the leakage interruption signal is adjusted to the first voltage when the word line enable signal is activated.
7 more elements
A semiconductor memory device, comprising:
- a plurality of sub-word lines;
- a plurality of sub-word line drivers each connected to corresponding sub-word lines, the sub-word lines, the sub-word line drivers connecting the corresponding sub-word lines to a first voltage in response to corresponding word line enable signals and sub-word line driving signals during a precharge operation;
- a plurality of driving signal generating circuits each connected to a corresponding sub-word line driver and configured to provide the sub-word line driving signals thereto;
- and
- word line enable drivers each connected to a corresponding sub-word line driver and configured to provide the word line enable signals thereto,
- wherein each of the driving signal generating circuits comprises:
- a driving input terminal connected to receive a lower decoding signal,
- a driving output terminal connected to output a corresponding sub-word line driving signal;
- a first driving pull-down unit connected to the driving output terminal and configured to pull down the driving output terminal to a second voltage in response to the lower decoding signal;
- a second driving pull-down unit configured to pull down the driving output terminal to the first voltage in response to a driving control signal that responds to the lower decoding signal;
- and
- a driving control unit configured to adjust the driving control signal to the first voltage in response to pull-up of the driving output terminal so as to at least substantially inhibit leakage current caused by the second driving pull-down unit.
9 more elements
A semiconductor memory device, comprising:
- a plurality of sub-word lines;
- a plurality of sub-word line drivers each connected to corresponding sub-word lines, the sub-word lines, the sub-word line drivers connecting the corresponding sub-word lines to a first voltage in response to corresponding word line enable signals and sub-word line driving signals during a precharge operation;
- a plurality of driving signal generating circuits each connected to a corresponding sub-word line driver and configured to provide the sub-word line driving signals thereto;
- and
- word line enable drivers each connected to a corresponding sub-word line driver and configured to provide the word line enable signals thereto,
- wherein each of the driving signal generating circuits comprises:
- a driving input terminal connected to receive a lower decoding signal,
- a driving output terminal connected to output a corresponding sub-word line driving signal;
- a first driving current path formed between the driving output terminal and the second voltage in response to the lower decoding signal;
- a second driving current path formed between the driving output terminal and the first voltage in response to a driving control signal that responds to the lower decoding signal;
- and
- a driving control unit configured to adjust the driving control signal to the first voltage in response to pull-up of the driving output terminal so as to at least substantially inhibit leakage current caused by the second driving current path.
9 more elements
A semiconductor memory device, comprising:
- a plurality of sub-word lines;
- a plurality of sub-word line drivers each connected to corresponding sub-word lines, the sub-word line drivers connecting the corresponding sub-word lines to a first voltage in response to corresponding word line enable signals and sub-word line driving signals during a precharge operation;
- a plurality of driving signal generating circuits each connected to a corresponding sub-word line driver and configured to provide the sub-word line driving signals thereto;
- and
- word line enable drivers each connected to a corresponding sub-word line driver and configured to provide the word line enable signals thereto,
- wherein each of the driving signal generating circuits comprises:
- a driving input terminal connected to receive a lower decoding signal;
- a driving output terminal connected to output a corresponding sub-word line driving signal;
- a first inverter connected to receive the lower decoding signal and configured to output an inverted signal therefrom;
- a second inverter connected to receive the lower decoding signal and configured to output an inverted signal therefrom;
- a driving pull-up unit configured to pull up the driving output terminal to a boosting voltage in response to the output signal of the first inverter;
- a first driving pull-down unit configured to pull down the driving output terminal to a second voltage in response to the output signal of the first inverter and a signal of the driving output terminal;
- a second driving pull-down unit configured to pull down the driving output terminal to the first voltage in response to a driving control signal that responds to the output signal of the second inverter;
- and
- a driving control unit configured to adjust the driving control signal to the first voltage in response to pull-up of the driving output terminal so as to at least substantially inhibit leakage current caused by the second driving pull-down unit.
12 more elements
A method of driving a semiconductor memory device including at least one sub-word line driver configured to connect a corresponding sub-word line to a first voltage in response to a word line enable signal and a sub-word line driving signal, the method comprising:
- generating by a driving signal generating circuit the sub-word line driving signal and providing the sub-word line driving signal to a corresponding sub-word line driver through a driving output terminal, the driving signal generating circuit having a driving input terminal and the driving output terminal;
- and
- generating by a word line enable driver a pulled down word line enable signal in response to a decoder control terminal and providing the word line enable signal to the corresponding sub-word line driver, the word line enable driver having a decoder input terminal and the decoder control terminal,
- wherein generating by a driving signal generating circuit comprises:
- receiving a lower decoding signal;
- pulling down the sub-word line driving signal to a second voltage in response to the lower decoding signal;
- and
- pulling down the sub-word line driving signal to the first voltage in response to a predetermined driving control signal,
- wherein the driving control signal is adjusted to the first voltage in response to pull-up of the driving output terminal.
6 more elements
A method of driving a semiconductor memory device including at least one sub-word line driver configured to connect a corresponding sub-word line to a first voltage in response to a word line enable signal and a sub-word line driving signal, the method comprising:
- generating by a driving signal generating circuit the sub-word line driving signal and providing the sub-word line driving signal to a corresponding sub-word line driver through a driving output terminal, the driving signal generating circuit having a driving input terminal and the driving output terminal;
- and
- generating by a word line enable driver a pulled down word line enable signal in response to a decoder control terminal and providing the word line enable signal to the corresponding sub-word line driver, the word line enable driver having a decoder input terminal and the decoder control terminal,
- wherein generating by a driving signal generating circuit comprises:
- receiving a lower decoding signal through the driving input terminal;
- forming a first driving current path between the driving output terminal and a second voltage in response to the lower decoding signal;
- and
- forming a second driving current path between the driving output terminal and the first voltage in response to a predetermined driving control signal,
- wherein the driving control signal is adjusted to the first voltage in response to pull-up of the driving output terminal.
6 more elements
Dependencies are inferred from the claim text.