US 7,248,534 B2Granted

Semiconductor memory device

AssigneeFujitsu Limited

InventorsHiroshi Shimizu, Wataru Yokozeki

Life of this patent

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Abstract

A semiconductor memory device that speeds up its operation. A multiplexer puts one of word lines into an active state to select one memory cell in each local block. Another multiplexer puts one of local block selection signals into an active state and puts one of p-channel transistors into the ON state to select one of local blocks arranged in a column direction. A NAND element inverts the logical product of a signal output from a local block selected by a local block selection signal and a signal output from a block not selected and outputs a result obtained to put an n-channel transistor into the ON or OFF state. The n-channel transistor grounds a common bit line when it goes into the ON state. Each of the p-channel transistors is selected by a column switch (not shown) and send read data to a data bus.

Claims1

Dependent claims

A semiconductor memory device in which memory cells arranged in a column direction are divided into a plurality of local blocks, in which data is read or written by the local block, and in which each local block has a write error protection circuit for preventing a write error from occurring in the case of data being written into a memory cell, the write error protection circuit including:

a first transistor to an input terminal of which an auxiliary common bit line for reading data from or writing data into a local block included in each column is connected, to a first output terminal of which a main connection line of a memory cell included in the local block is connected, and to a second output terminal of which power supply is connected;
and
a second transistor to an input terminal of which a main common bit line for reading data from or writing data into a local block included in each column is connected, to a first output terminal of which an auxiliary connection line of a memory cell included in the local block is connected, and to a second output terminal of which the power supply is connected.

Dependencies are inferred from the claim text.

Facts

Application: 11/312,586Filed 21 Dec 2005 · division
Priority: JP 2001-3444919 Nov 2001
Published: US 2006/0098517 A111 May 2006
Granted: 24 Jul 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 11/413
Forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt…
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 8/08
Arrangements for selecting an address in a digital store: word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down…
G11C 8/10
Arrangements for selecting an address in a digital store: decoders

Family

Application10/199,070Parent of this division · filed 22 Jul 2002
Application11/055,969Parent of this division · filed 14 Feb 2005
US 2006/0098517 A1Pre-grant publication · published 11 May 2006
US 7,016,238 B2Parent of this division
US 6,870,788 B2Parent of this division
US 2003/0090944 A1Published application
US 2005/0146976 A1Published application
US 7,248,534 B2This patent

From the US filing history. Foreign family members aren’t listed.