Refresh control method of a semiconductor memory device and semiconductor memory device

A semiconductor memory device comprising:

• an array circuit having a plurality of memory cells disposed at intersections of word lines corresponding to row addresses and bit lines corresponding to column addresses,
• a peripheral circuit including control means for controlling operation of said array circuit,
• voltage generating means for generating at least one array voltage of an array power supply to be supplied to said array circuit and at least one peripheral voltage of a peripheral power supply to be supplied to said peripheral circuit,
• self-refresh control means for controlling a self-refresh operation in which said memory array is divided into a holding area used as a copy source which includes memory cells on a predetermined number of word lines and a copy area used as a copy destination which includes memory cells on word lines to which entire data of said holding area is to be copied, copy operation in which data of each memory cell of said holding area is copied to one or more memory cells in said copy area on the same bit line or the same pair of bit lines is executed, and said self-refresh operation in which a row address of said holding area is designated and a corresponding word line is selected and driven, and at the same time, one or more word lines in said copy area corresponding to said selected word line are selected and driven is executed, and
• power supply control means for controlling switching of said array power supply and said peripheral power supply such that supply or suspension of said array voltage and said peripheral voltage is switched in accordance with a state of said self-refresh operation.