Static random access memory (SRAM) with replica cells and a dummy cell

A semiconductor memory device, comprising:

• a memory array including plural memory cells connected with a word line and a bit line;
• a sense amplifier circuit which amplifies data read from one memory cell of said memory array to said bit line;
• a replica circuit which includes plural stages of replica cells having the same elements as each one of said plural memory cells and connected with a common replica bit line, and which outputs to said common replica bit line a signal which is at a level which corresponds to the number of said plural stages of replica cells;
• a dummy cell which is connected as a load with said common replica bit line;
• and
• a sense amplifier control circuit which receives said signal on said replica bit line and controls the timing of a signal which starts up said sense amplifier circuit,
• wherein said dummy cell comprises a first, a second, a third and a fourth transistors of a first conductive type and a first and a second transistors of a second conductive type,
• the drain, the gate and the source of said first transistor of said first conductive type are connected respectively with said replica bit line, a first constant voltage source and a first node,
• the drain, the gate and the source of said second transistor of said first conductive type are connected respectively with said first node, a second node and a second constant voltage source,
• the drain and the source of said third transistor of said first conductive type are connected respectively with a replica bit bar line and said second node,
• the drain, the gate and the source of said fourth transistor of said first conductive type are connected respectively with said second node, said first node and said second constant voltage source,
• the drain, the gate and the source of said first transistor of said second conductive type are connected respectively with said first node, said second node and said second constant voltage source, and
• the drain, the gate and the source of said second transistor of said second conductive type are connected respectively with said second node, said first node and said second constant voltage source.