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US 7,248,522 B2Granted
Sense amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM)
AssigneesUnited Memories, Inc., Sony Corporation
InventorKim C. Hardee
Life of this patent
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Abstract
A sense amplifier power-gating circuit and method is disclosed which is of particular utility with respect to DRAM devices, or those incorporating embedded DRAM, and having a power-down (or Sleep) mode of operation. In accordance with a particular technique of the present invention, the local sense amplifier driver transistors serve a dual purpose as both driver and power gate transistors thereby obviating the need for large, distinct power-gating devices. This serves to minimize on-chip area requirements while not degrading sensing speed as in conventional approaches.
Claims38
An integrated circuit device including a memory array comprising:
- at least one sense amplifier having Active, Standby and Sleep modes thereof coupled to complementary bit lines, said sense amplifier having first and second voltage nodes thereof;
- a first transistor coupling said first voltage node to a first voltage source, a control terminal of said first transistor being coupled to receive a first control signal;
- and
- a second transistor coupling said second voltage node to a second voltage source, a control terminal of said second transistor being coupled to receive a second control signal,
- wherein, in a Standby Mode of operation, said first control signal is substantially at a level of said first voltage source and said second control signal is substantially at a level of said second voltage source and
- wherein, in a Sleep Mode of operation, said first control signal is substantially at a level greater than said first voltage source and said second control signal is substantially at a level lower than said second voltage source.
3 more elements
An integrated circuit device including a memory array comprising:
- at least one CMOS sense amplifier coupled to complementary bit lines and including a latch P-channel (LP) and latch N-channel (LN) nodes thereof;
- a first transistor coupled between a supply voltage source and said LP node and having a control terminal thereof coupled to receive an LPB signal;
- a second transistor coupled between a reference voltage source and said LN node and having a control terminal thereof coupled to receive an LNB signal wherein said LPB and said LNB signals present Active, Standby and Sleep states thereof wherein,
- in a Sleep Mode of operation, said LPB signal is substantially at a level greater than that of said supply voltage source and said LNB signal is substantially at a level lesser than that of said reference voltage source.
1 more element
A method for power-gating in an integrated circuit device incorporating a memory having a plurality of sense amplifiers comprising:
- providing first and second transistors for coupling first and second shared voltage nodes respectively of said plurality of sense amplifiers to respective first and second voltage sources;
- enabling said first and second transistors in an Active Mode of operation to couple said first and second shared voltage nodes to said first and second voltage sources respectively;
- disabling said first and second transistors in a Standby Mode of operation to decouple said first and second shared voltage nodes from said first and second voltage nodes respectively;
- and
- further disabling said first and second transistors in a Sleep Mode of operation by applying a voltage greater than that of said first voltage source to a control terminal of said first transistor and a voltage lesser than that of said second voltage source to a control terminal of said second transistor.
2 more elements
An integrated circuit device including a memory array comprising:
- a plurality of sense amplifiers coupled to respective complementary bit lines, each of said plurality of sense amplifiers including first and second shared nodes thereof;
- a first transistor coupled between a supply voltage source and said first shared node and having a control terminal thereof coupled to receive a first signal;
- a second transistor coupled between a reference voltage source and said second shared node and having a control terminal thereof coupled to receive a second signal wherein said first and said second signals present Active, Standby and Sleep states thereof wherein, in a Sleep Mode of operation, said first signal is substantially at a level greater than that of said supply voltage source and said second signal is substantially at a level lesser than that of said reference voltage source.
An integrated circuit device including a memory array comprising:
- at least one CMOS sense amplifier coupled to complementary bit lines and including a latch P-channel (LP) and latch N-channel (LN) nodes thereof;
- a first transistor coupled between a supply voltage source and said LP node and having a control terminal thereof coupled to receive an LPB signal;
- a second transistor coupled between a reference voltage source and said LN node and having a control terminal thereof coupled to receive an LNB signal wherein said LPB and said LNB signals each present Active, Standby and Sleep states thereof corresponding to three different voltage levels.
An integrated circuit device including a memory array comprising:
- a plurality of sense amplifiers coupled to respective complementary bit lines, each of said plurality of sense amplifiers including first and second shared nodes thereof;
- a first transistor coupled between a supply voltage source and said first shared node and having a control terminal thereof coupled to receive a first signal;
- a second transistor coupled between a reference voltage source and said second shared node and having a control terminal thereof coupled to receive a second signal wherein said first and said second signals each present Active, Standby and Sleep states thereof corresponding to three different voltage levels.
Dependencies are inferred from the claim text.