Negative voltage discharge scheme to improve snapback in a non-volatile memory
AssigneeMicron Technology, Inc.
InventorsVipul Patel, Stephen Gualandri
Life of this patent
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Abstract
Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transistors until the discharging voltage reaches a first voltage level. The path through the pair of discharge transistors is controlled by an intermediate control voltage so that none of the transistors of the pair enter the snapback condition. In the second discharge period, the remaining discharging voltage is fully discharged from the first level through a third discharge transistor.
Claims36
A discharge circuit for a memory device, said circuit for discharging a first voltage having a first potential, said circuit comprising:
- a first discharge circuit for discharging the first voltage from the first potential to a second potential during a first discharge time;
- and
- a second discharge circuit for discharging the first voltage from the second potential to a third potential during a second discharge time.
A memory device comprising:
- an array of memory cells;
- a charge pump for providing an output voltage on an output line connected to said array, said output voltage having a first potential;
- and
- a discharge circuit coupled to the output voltage, said circuit comprising:
- a first discharge circuit for discharging the output voltage from the first potential to a second potential during a first discharge time, and
- a second discharge circuit for discharging the output voltage from the second potential to a third potential during a second discharge time.
A system comprising:
- a processor coupled to a memory device, said memory device comprising:
- an array of memory cells;
- a charge pump for providing an output voltage on an output line to said array, said output voltage having a first potential;
- and
- a discharge circuit coupled to the output voltage, said circuit comprising:
- a first discharge circuit for discharging the output voltage from the first potential to a second potential during a first discharge time, and
- a second discharge circuit for discharging the output voltage from the second potential to a third potential during a second discharge time.
A method of discharging a voltage having a first potential in a memory device, said method comprising the acts of:
- discharging the first voltage from the first potential to a second potential during a first discharge time;
- and
- discharging the first voltage from the second potential to a third potential during a second discharge time.
Dependencies are inferred from the claim text.