Non-volatile memory with test rows for disturb detection
AssigneeMicron Technology, Inc.
InventorChristophe J. Chevallier
Life of this patent
Estimating the term…
Abstract
A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test rows are not externally accessible for standard program and read operations. The test rows are located near bit line driver circuitry to insure the highest exposure to bit line voltages that may disturb memory cells in the array.
Claims23
A memory device comprising:
- an array of memory cells arranged in rows and columns;
- a plurality of bit lines coupled to the memory cells;
- a driver circuit coupled to the plurality of bit lines;
- and
- one or more test rows located adjacent to the driver circuit;
- wherein the one or more test rows are not externally addressable for programming and reading.
A non-volatile memory device, comprising:
- an array of reprogrammable non-volatile memory cells arranged in rows and columns;
- a plurality of bit lines coupled to the non-volatile memory cells;
- a driver circuit coupled to the plurality of bit lines;
- and
- a means for detecting memory cell disturb coupled to the array;
- and
- wherein the means for detecting memory cell disturb is located adjacent to the driver circuit.
A method of testing for memory cell disturb in a memory device, comprising:
- performing a disturb test operation on one or more test rows of memory cells located adjacent to a driver circuit to forecast a lack of memory cell disturb of memory cells located in an addressable array of memory cells.
Dependencies are inferred from the claim text.