Semiconductor memory device having memory block configuration

A semiconductor memory device, comprising:

• a plurality of memory blocks, each having a normal block and a spare block;
• a region for storing memory array storing block information formed of spare block replacement information for each of said plurality of memory blocks and defective spare block information;
• a spare block determination circuit receiving said block information and outputting a spare block determination signal determining whether said plurality of memory blocks are normal or defective;
• and
• a decode circuit receiving said spare block determination signal and performing decoding for each of said plurality of memory blocks, wherein
• said decode circuit includes a block address register receiving said spare block determination signal in response to a strobe signal.

A semiconductor memory device, comprising:

• a non-volatile memory array having a plurality of banks,
• at least one of said plurality of banks includes
• a first region having normal block regions and a spare block region, each of said normal block regions is a unit of batch erase, and said spare block region is used as a normal block region when said normal block region is defective, and
• a second region having a boot block region that is a unit of batch erase smaller than said normal block region.