Semiconductor memory device having controller with improved current consumption
AssigneeHynix Semiconductor Inc.
InventorBeom Ju Shin
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device wherein, in order to control the current consumed in a column address counter and latch block in a read operation, delay units disposed in the column address counter and latch block perform a shifting operation according to a signal CASP6, which is enabled in the write and read operations, and a signal WT6RD5Z, which is enabled in the write operation and disabled in the read operation. Accordingly, unnecessary current consumed in the read operation can be reduced.
Claims19
A semiconductor memory device including delay circuits for delaying a bank address and a column address in a write operation, the semiconductor memory device comprising:
- a controller for disabling the operation of the delay circuits in a read operation.
A memory device comprising:
- at least one delay circuit for delaying a bank address and a column address in a write operation;
- and a controller for disabling the operation of the delay circuits in a read operation.
A memory device comprising:
- a plurality of delay delay circuits for delaying a bank address and a column address in a write operation, the semiconductor memory device comprising:
- a controller for disabling the operation of the delay circuits in a read operation wherein the plurality of the delay circuits are disposed in a plurality of column address counter and latches are controlled at the same time according to an output of the controller.
A semiconductor device comprising:
- a memory device, comprising:
- at least one delay circuit for delaying a bank address and a column address in a write operation;
- and a controller for disabling the operation of the delay circuits in a read operation.
Dependencies are inferred from the claim text.