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US 7,248,511 B2Granted
Random access memory including selective activation of select line
AssigneeInfineon Technologies AG
InventorMargaret Freebern
Life of this patent
Estimating the term…
Abstract
A random access memory that includes an array of memory cells, a first circuit configured to receive an address to address memory cells in the array of memory cells, and a second circuit. The second circuit is configured to obtain control signals including an address strobe signal and gate the address strobe signal using other control signals to provide a gated address strobe signal and to control activation of a select line signal based on the gated address strobe signal.
Claims31
A random access memory, comprising:
- an array of memory cells;
- a first circuit configured to receive an address to address memory cells in the array of memory cells;
- and
- a second circuit configured to obtain control signals including an address strobe signal and a data mask signal and to gate the address strobe signal via the data mask signal to provide a gated address strobe signal and to control activation of a select line signal based on the gated address strobe signal.
1 more element
A computer system, comprising:
- a processor;
- and
- a random access memory configured to receive row addresses and column addresses and control signals via the processor, the random access memory comprising:
- an array of memory cells;
- a row decoder configured to receive the row addresses via the processor to address selected memory cells in the array of memory cells;
- a column decoder configured to receive the column addresses via the processor to address the selected memory cells in the away of memory cells;
- and
- a control circuit configured to obtain the control signals via the processor and to obtain a column address strobe signal and a data mask signal and to gate the column address strobe signal via the data mask signal to provide a gated column address strobe signal and to selectively activate a column select line signal based on the gated column address strobe signal.
5 more elements
A random access memory, comprising:
- an array of memory cells;
- a first circuit configured to receive addresses to address memory cells in the array of memory cells;
- and
- a second circuit configured to check redundancy of the addresses and provide an adjacent segment redundancy signal that indicates if the addressed memory cells are to be replaced with spare memory cells in a different memory cell segment and to control activation of a select line signal based on to adjacent segment redundancy signal.
1 more element
A random access memory, comprising:
- means for receiving an address;
- means for addressing memory cells based on the received address;
- means for obtaining control signals including an address strobe signal and a data mask signal;
- means for gating the address strobe signal via the data mask signal;
- and
- means for controlling activation of a select line signal based on the gated address strobe signal.
3 more elements
A random access memory, comprising:
- means for receiving an address;
- means for addressing memory cells based on the received address;
- means for checking redundancy of the address to provide an adjacent segment redundancy signal that indicates if the addressed memory cells are to be replaced with spare memory cells in a different memory cell segment;
- and
- means for controlling activation of a select line signal based on the adjacent segment redundancy signal.
2 more elements
A method of controlling access to memory cells in a random access memory, comprising:
- receiving an address;
- addressing memory cells based on the received address;
- obtaining control signals including an address strobe signal and a data mask signal;
- gating the address strobe signal via the data mask signal;
- and
- controlling activation of a select line signal based on the gated address strobe signal.
3 more elements
A method of controlling access to memory cells in a computer system, comprising:
- receiving a row address and a column address via a processor;
- addressing selected memory cells in the array of memory cells using the row address;
- addressing selected memory cells in the array of memory cells using the column address;
- receiving control signals via the processor:
- obtaining a column address strobe signal;
- obtaining a data mask signal;
- gating the column address strobe signal via the data mask signal to provide a gated column address strobe signal;
- and
- activating a column select line signal based on the gated column address strobe signal.
6 more elements
A method of controlling access to memory cells in a random access memory, comprising:
- receiving an address;
- addressing memory cells based on the received address;
- checking redundancy of the address to provide an adjacent segment redundancy signal that indicates if the addressed memory cells are to be replaced with spare memory cells in a different memory cell segment;
- and
- controlling activation of a select line signal based on the adjacent segment redundancy signal.
2 more elements
A random access memory, comprising:
- an array of memory cells;
- a first circuit configured to receive an address to address memory cells in the array of memory cells;
- and
- a second circuit configured to obtain control signals including an address strobe signal, a data mask signal, and a write signal and gate the address strobe signal based on the data mask signal and the write signal to provide a gated address strobe signal and to control activation of a select line signal based on the gated address strobe signal and wherein the second circuit is configured to obtain an adjacent segment redundancy signal and to control activation of the select line signal based on the obtained adjacent segment redundancy signal.
1 more element
Dependencies are inferred from the claim text.