Circuits that generate an internal supply voltage and semiconductor memory devices that include those circuits

An internal supply voltage generation circuit within a semiconductor memory device and configured to generate an internal supply voltage to a memory array in the semiconductor memory device, the internal supply voltage generation circuit comprising:

• an internal driving unit configured to generate a driving current and a preliminary voltage responsive to an external supply voltage supplied from external to the semiconductor memory device, and configured to vary a magnitude of the driving current responsive to a driving control signal;
• an internal transmission unit configured to generate the internal supply voltage responsive to the preliminary voltage from the internal driving unit, and configured to vary a level of the internal supply voltage to be at least a defined voltage difference less than a boosted voltage, wherein the boosted voltage is greater than the external supply voltage;
• and
• an internal sensing unit configured to generate the driving control signal responsive to the preliminary voltage so that the internal supply voltage is maintained at a constant level.

A semiconductor memory device with a memory array of a plurality of memory cells that are powered by an internal supply voltage, the semiconductor memory device comprising:

• at least one PMOS transistor comprising a N-well of a bit line sense amplifier area configured to drive at least one bit line of the memory array, wherein a source terminal of the PMOS transistor is connected to the internal supply voltage;
• a boosting voltage generation circuit configured to generate a boosted voltage that is greater than an external supply voltage supplied from external to the semiconductor memory device, wherein the boosted voltage is supplied to the N-well of the bit line sense amplifier area;
• and
• an internal supply voltage generation circuit configured to generate the internal supply voltage responsive to the external supply voltage, and configured to vary a level of the internal supply voltage to be at least a defined voltage difference less than a voltage level of the N-well of the bit line sense amplifier area,
• wherein the internal supply voltage generation circuit comprises:
• an internal driving unit configured to generate a driving current and a preliminary voltage responsive to the external supply voltage and to vary a magnitude of the driving current responsive to a driving control signal;
• an internal transmission unit configured to generate the internal supply voltage responsive to the preliminary voltage from the internal driving unit, and configured to vary a level of the internal supply voltage to be at least a defined voltage difference less than the boosted voltage, wherein the boosted voltage is greater than the external supply voltage;
• and
• an internal sensing unit configured to generate the driving control signal responsive to the preliminary voltage so that the internal supply voltage is maintained at a constant level.

A semiconductor memory device with a memory array of a plurality of memory cells that are powered by an internal supply voltage, the semiconductor memory device comprising:

• at least one PMOS transistor comprising a N-well of a bit line sense amplifier area configured to drive at least one bit line of the memory array, wherein a source terminal of the PMOS transistor is connected to the internal supply voltage;
• a boosting voltage generation circuit configured to generate a boosted voltage that is greater than an external supply voltage supplied from external to the semiconductor memory device, wherein the boosted voltage is supplied to the N-well of the bit line sense amplifier area;
• and
• an internal supply voltage generation circuit configured to generate the internal supply voltage responsive to the external supply voltage, and configured to vary a level of the internal supply voltage to be at least a defined voltage difference less than a voltage level of the N-well of the bit line sense amplifier area,
• wherein the internal supply voltage generation circuit comprises:
• an internal driving unit configured to generate a driving current and a preliminary voltage responsive to the external supply voltage and to vary a magnitude of the driving current responsive to a driving control signal;
• an internal transmission unit configured to generate the internal supply voltage responsive to the preliminary voltage from the internal driving unit, and configured to vary a level of the internal supply voltage to be at least a defined voltage difference less than the boosted voltage, wherein the boosted voltage is greater than the external supply voltage;
• and
• an internal sensing unit configured to generate the driving control signal responsive to the internal supply voltage so that the internal supply voltage is maintained at a constant level.

A semiconductor memory device with a memory array of a plurality of memory cells that are powered by an internal supply voltage, the semiconductor memory device comprising:

• at least one PMOS transistor comprising a N-well of a bit line sense amplifier area configured to drive at least one bit line of the memory array, wherein a source terminal of the PMOS transistor is connected to the internal supply voltage;
• a boosting voltage generation circuit configured to generate a boosted voltage that is greater than an external supply voltage supplied from external to the semiconductor memory device, wherein the boosted voltage is supplied to the N-well of the bit line sense amplifier area;
• an internal supply voltage generation circuit configured to generate the internal supply voltage responsive to the external supply voltage, and configured to vary a level of the internal supply voltage to be at least a defined voltage difference less than a voltage level of a transmission control node;
• and
• a boosting transmission circuit configured to supply the boosted voltage from the boosting voltage generation circuit to the transmission control node of the internal supply voltage generation circuit.

A semiconductor memory device with a memory array of a plurality of memory cells that are powered by an internal supply voltage, the semiconductor memory device comprising:

• at least one PMOS transistor comprising a N-well of a bit line sense amplifier area configured to drive at least one bit line of the memory array, wherein a source terminal of the PMOS transistor is connected to the internal supply voltage;
• a boosting voltage generation circuit configured to generate a boosted voltage that is greater than an external supply voltage supplied from external to the semiconductor memory device, wherein the boosted voltage is supplied to the N-well of the bit line sense amplifier area;
• and
• an internal supply voltage generation circuit configured to generate the internal supply voltage responsive to the external supply voltage, and configured to vary a level of the internal supply voltage to be at least a defined voltage difference less than a voltage level of a transmission control node, wherein the transmission control node is electrically connected to the N-well of the bit line sense amplifier area.