Circuit arrangement having security and power saving modes

A circuit arrangement comprising:

• complementary data input nodes for reception of a dual rail data signal;
• complementary data output nodes for outputting a dual rail data signal;
• and
• means for production of a potential balance state, in which the potentials at the complementary data output nodes are the same and are in an intermediate range between a high signal level and a low signal level,
• wherein a connection switch is connected to complementary data nodes by means of which the complementary data nodes can be connected to one another with a low resistance,
• wherein a control unit is provided for generating a first control signal for the connection switch, and
• wherein the circuit arrangement is designed to be operated in a power saving mode, in which the connection switch is switched by the control unit to have a high resistance, and in a security node, in which the connection switch is switched by the control unit to have a low resistance when the potential at the complementary data nodes is intended to be equalized.