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US 7,248,505 B2Granted
Flash memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsMyong-Jae Kim, Doo-Sub Lee
Life of this patent
Estimating the term…
Abstract
A flash memory device includes a write driver for driving a data line according to data to be written in a flash memory cell during a program period, a sense amplifier circuit for sensing and amplifying the data stored in the flash memory cell during a program verify period, and an insulation circuit for electrically insulating the sense amplifier circuit from the data line during an operation period of the write driver.
Claims29
A semiconductor integrated circuit device comprising:
- a high voltage circuit operating with a high voltage;
- a low voltage circuit operating with a low voltage;
- an internal circuit connected to the high and low voltage circuits through a signal line;
- and
- a first isolation circuit for electrically isolating the low voltage circuit from the signal line during an operation period of the high voltage circuit, the first isolation circuit being coupled between the signal line and the low voltage circuit, wherein the first isolation circuit includes a MOS transistor having a breakdown voltage higher than the high voltage.
2 more elements
A semiconductor integrated circuit device comprising:
- a high voltage circuit operating with a high voltage;
- a low voltage circuit operating with a low voltage;
- an internal circuit connected to the high and low voltage circuits through a signal line;
- a first isolation circuit for electrically isolating the low voltage circuit from the signal line during an operation period of the high voltage circuit, the first isolation circuit being coupled between the signal line and the low voltage circuit;
- and
- a second isolation circuit for electrically isolating the high voltage circuit from the signal line, the second isolation circuit being coupled between the signal line and the high voltage circuit, wherein the second isolation circuit includes a MOS transistor having a breakdown voltage higher than the high voltage.
3 more elements
A flash memory device comprising:
- a flash memory cell;
- a bit line connected to the flash memory cell;
- a switch circuit for connecting the bit line to a data line;
- a write driver for driving the bit line with a high voltage according to data to be stored in the flash memory cell, the write driver being connected to the data line;
- a sense amplifier circuit for sensing data stored in the flash memory cell through the bit line, the sense amplifier circuit being connected to the data line;
- and
- a first isolation circuit for isolating the sense amplifier circuit from the data line during an operation period of the write driver.
4 more elements
A flash memory device comprising:
- sectors each including local bit lines, wherein flash memory cells are connected in parallel to the respective local bit lines;
- a column selection circuit for selecting one of the sectors to connect bit lines of the selected sector to corresponding global bit lines respectively;
- a first switch circuit for connecting the global bit lines to data lines during a program operation;
- a write driver circuit for driving the data lines with a high voltage according to data to be stored in the selected sector during the program operation;
- a sense amplifier circuit for sensing data stored in the selected sector through the data lines and the selected bit lines during a program verify operation;
- a second switch circuit coupled between the data lines and the sense amplifier circuit;
- and
- a control circuit for controlling the second switch circuit to isolate the sense amplifier circuit from the data lines during the program operation.
5 more elements
A flash memory device comprising:
- sectors each including local bit lines, wherein flash memory cells are connected in parallel to the respective local bit lines;
- a column selection circuit for selecting one of the sectors to connect bit lines of the selected sector to corresponding global bit lines respectively;
- a first switch circuit that is operable in a first mode to connect the global bit lines to first data lines during a program operation and in a second mode to connect the global bit lines to second data lines during a read operation;
- a write driver circuit for driving the first data lines with a high voltage according to data to be stored in the selected sector during the program operation;
- a first sense amplifier circuit for sensing data stored in the selected sector through the first data lines and the selected bit lines during a program verify operation;
- a second sense amplifier circuit for sensing data stored in the selected sector through the second data lines and the selected bit lines during the read operation;
- a second switch circuit coupled between the first data lines and the first sense amplifier circuit;
- and
- a control circuit for controlling the second switch circuit to isolate the first sense amplifier circuit from the first data lines during the program operation and controlling a third switch circuit to isolate the write driver from the first data lines during the program verify operation.
6 more elements
Dependencies are inferred from the claim text.