Layout for NAND flash memory array having reduced word line impedance

A non-volatile memory device, comprising:

• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the non-volatile memory device, the command decoder further operable to generate control signals corresponding to the decoded command signals;
• an address circuit operable to receive a memory address;
• a memory array of non-volatile memory cells, the memory array comprising:
• a first region in which a first memory sub-array is located, the first memory sub-array having NAND flash memory cells coupled to word lines and bit lines corresponding to rows and columns of memory cells;
• a second region separated from the first region in which a second memory sub-array is located, the second memory sub-array having NAND flash memory cells coupled to word lines and bit lines corresponding to rows and columns of memory cells;
• a driver region in which word line driver circuits and first row decoder sub-circuits are located, the driver region separating the first and second regions, the word line drivers coupled to the word lines from the first memory sub-array and the word lines from the second memory sub-array and configured to drive the respective word lines responsive to a drive signal and each first row decoder sub-circuit configured to generate a drive signal for a respective word line driver circuits responsive to an enable signal;
• and
• a row decoder region in which row decoder circuits coupled to the address circuit are located, the row decoder region adjacent the first region and separated from the driver region by the first region, each row decoder circuit including a second row decoder sub-circuit coupled to a respective first row decoder sub-circuit and configured to generate the enable signal in response to decoding address signals selecting the particular row decoder circuit,
• a column decoder coupled to the memory array and operable to access a selected column page from the memory array;
• and
• a read data path circuit coupled to the column decoder and operable to couple read data signals from the memory cell array to external data terminals of the memory device.

A method for arranging a memory array for a NAND flash non-volatile memory, the method comprising:

• dividing the memory array into at least two memory sub-arrays, each memory sub-array having memory cells arranged in a NAND flash memory architecture with word lines and bit lines corresponding to rows and columns of memory;
• separating a first and a second memory sub-array by a first region in which drive circuits coupled to the word lines of the first and second memory sub-arrays, the drive circuits driving selected word lines of the first and second memory sub-arrays responsive to selection by the first row decoder sub-circuits;
• locating first row decoder sub-circuits in a second region separated from the first region by at least one of the memory sub-arrays, the row decoder circuits coupled to a respective one of the drive circuits located in the first region to select the respective drive circuit in response to decoding a memory address identifying a corresponding row decoder circuit;
• and
• locating second row decoder sub-circuits in the first region, the second row decoder sub-circuits coupled to a respective drive circuit in the first region and a respective first row decoder sub-circuit located in the second region, and selecting a first row decoder sub-circuit in response to decoding address signals, the first row decoder sub-circuit enabling a respective second row decoder sub-circuit to activate a respective drive circuit to drive the word lines coupled to the activated drive circuit.