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US 7,248,498 B2Granted
Serial transistor-cell array architecture
AssigneeMicron Technology, Inc.
InventorHagop A. Nazarian
Life of this patent
Estimating the term…
Abstract
A memory device having memory cells in which a single access transistor controls the grounding of at least four storage elements, such as resistive storage elements, for purposes of reading the respective logical states of the storage elements. Unique sensing techniques are provided to sense the states of the storage elements. The logical states of the storage elements are decoupled from one another and are read independently.
Claims21
A memory device comprising:
- a memory array, said memory array comprising a plurality of memory blocks, each block comprising at least four resistive memory cells and a transistor, each memory cell having a first terminal electrically connected to a first side of said transistor and a second terminal coupled to a respective bit line that is different from bit lines connected to the other memory cells in said block such that each memory cell in a block is coupled between its respective bit line and the first side of the transistor, each transistor having a second side connected to a sense line and a gate connected to a word line,
- wherein a resistance state of an addressed cell is sensed through a resistance path comprising the sense line, transistor, addressed cell and the respective bit line connected to the addressed cell.
A memory device, comprising:
- a memory array comprising a plurality of resistive variable memory cells;
- and
- means within said array for forming an electrical circuit between an addressed memory cell and at least three other memory cells, said circuit comprising a transistor electrically coupling said addressed memory cell and the other memory cells to a sense line;
- and
- means for sensing a resistance state of the addressed cell through the circuit, wherein the addressed memory cell is in electrical communication with a first bit line, and the other memory cells are in electrical communication with respective second, third and fourth bit lines and the transistor and sensing means sensing the resistance state through a resistance path comprising the sense line, transistor, addressed cell and first bit line.
2 more elements
A memory device, comprising:
- a memory array comprising a plurality of resistive variable memory cells;
- means within said array for forming an electrical circuit between an addressed memory cell and at least three other memory cells, said circuit comprising a transistor electrically coupling said addressed memory cell and the other memory cells to a sense line;
- means for sensing a resistance state of the addressed cell through the circuit, wherein the addressed memory cell is in electrical communication with a first bit line, and the other memory cells are in electrical communication with respective second, third and fourth bit lines, and sensing means sensing the resistance state through a resistance path comprising the sense line, transistor, addressed cell and first bit line;
- means for reading a first value from the addressed cell;
- means for writing a second value into the addressed cell;
- means for reading the second value from the addressed cell;
- and
- means for determining if the first value is the same as the second value.
5 more elements
A memory device, comprising:
- a memory array comprising a plurality of resistive variable memory cells;
- means within said array for forming an electrical circuit between an addressed memory cell and at least three other memory cells, said circuit comprising a transistor electrically coupling said addressed memory cell and the other memory cells to a sense line;
- means for sensing a resistance state of the addressed cell through the circuit, wherein the addressed memory cell is in electrical communication with a first bit line, and the other memory cells are in electrical communication with respective second, third and fourth bit lines, and sensing means sensing the resistance state through a resistance path comprising the sense line, transistor, addressed cell and first bit line;
- and
- a cascode transistor coupled to a first voltage source to limit a voltage on a bit line coupled to the addressed cell.
2 more elements
A processing system, comprising:
- a processor coupled to a memory device, said memory device comprising:
- a memory array, said memory array comprising a plurality of memory blocks, each block comprising at least four resistive memory cells and a transistor, each memory cell having a first terminal electrically connected to a first side of said transistor and a second terminal coupled to a respective bit line that is different from bit lines connected to the other memory cells in said block such that each memory cell in a block is coupled between its respective bit line and the first side of the transistor, each transistor having a second side connected to a sense line and a gate connected to a word line,
- wherein a resistance state of an addressed cell is sensed through a resistance path comprising the sense line, transistor, addressed cell and the respective bit line connected to the addressed cell.
A computer system, comprising:
- a processor coupled to a memory device, said memory device comprising:
- a memory array comprising a plurality of resistive variable memory cells;
- and
- means within said array for forming an electrical circuit between an addressed memory cell and at least three other memory cells, said circuit comprising a transistor electrically coupling said addressed memory cell and the other memory cells to a sense line;
- and
- means for sensing a resistance state of the addressed cell through the circuit, wherein the addressed memory cell is in electrical communication with a first bit line, and the other memory cells are in electrical communication with respective second, third and fourth bit lines and the transistor, and sensing means sensing the resistance state through a resistance path comprising the sense line, transistor, addressed cell and first bit line.
3 more elements
Dependencies are inferred from the claim text.