Back to results
US 7,248,493 B2Granted
Memory system having improved random write performance
AssigneeKabushiki Kaisha Toshiba
InventorsDaisaburo Takashima, Shuso Fujii, Takuya Futatsuyama, Takaya Suda, Masaki Momodomi
Life of this patent
Estimating the term…
Abstract
A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit and larger than a page as a program unit. The ferroelectric memory stores a logical address-physical address conversion table using the write unit.
Claims18
A memory system comprising:
- a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and a cell transistor;
- a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and configured to electrically erase and write data;
- a control circuit configured to control the ferroelectric memory and the flash EEPROM;
- and
- an interface circuit configured to communicate externally,
- wherein data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit and larger than a page as a program unit, and
- the ferroelectric memory stores a logical address-physical address conversion table using the write unit.
4 more elements
A memory system comprising:
- a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and a cell transistor;
- a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and configured to electrically erase and write data;
- a control circuit configured to control the ferroelectric memory and the flash EEPROM;
- and
- an interface circuit configured to communicate externally,
- wherein data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit, and
- the ferroelectric memory stores a logical address-physical address conversion table using the write unit.
4 more elements
Dependencies are inferred from the claim text.