Circuit for and method of implementing a content addressable memory in a programmable logic device

A circuit for implementing a content addressable memory in a programmable logic device, said circuit comprising:

• a first port having a read logic circuit and a write logic circuit, wherein said read logic circuit is configurable to have a read width of said first port, and said write logic circuit is configurable to have a write width of said first port which is different than said read width of said first port;
• a first output coupled to said first port, said first output generating a first portion of a word from said content addressable memory;
• a second port having a read logic circuit and a write logic circuit, wherein said read logic circuit is configurable to have a read width of said second port, and said write logic circuit is configurable to have a write width of said second port which is different than said read width of said second port;
• and
• a second output coupled to said second port, said second output generating a second portion of said word from said content addressable memory.

A circuit for implementing a content addressable memory in a programmable logic device, said circuit comprising:

• a first port having a read logic circuit and a write logic circuit, said first port having a write enable input and receiving a write enable signal;
• a first output coupled to said first port, said first output generating a first portion of a word from said content addressable memory;
• a second port having a read logic circuit and an enable input, said enable input receiving an inverted write enable signal;
• and
• a second output coupled to said second port, said second output generating a second portion of said word from said content addressable memory.

A method of accessing data in a content addressable memory of a programmable logic device, said method comprising the steps of:

• providing a first port of a dual port content addressable memory, said first port having a read logic circuit and a write logic circuit;
• configuring said read logic circuit to have a read width;
• configuring said write logic circuit to have a write width which is different than said read width;
• enabling said first port;
• receiving a write enable signal at said first port;
• providing a second port having a read logic circuit;
• and
• disabling said second port when said write enable signal enables writing to said first port.

A method of accessing data in a content addressable memory of a programmable logic device, said method comprising the steps of:

• providing a random access memory having a first port and a second port, each port having a read logic circuit and a write logic circuit;
• configuring said read logic circuit of said first port to have a read width;
• configuring said write logic circuit of said first port to have a write width which is different than said read width;
• enabling reading a first portion of a word by way of the read logic circuit of said first port;
• enabling reading a second portion of said word by way of the read logic circuit of said second port;
• outputting said word from said first port and said second port of said random access memory.

A method of accessing data in a content addressable memory of a programmable logic device, said method comprising the steps of:

• configuring a first port of a random access memory to have a write width for writing data;
• configuring said first port of said random access memory to have a read width for reading data, said read width being different than said write width;
• writing said data having said write width to said first port of said random access memory;
• and
• reading data having said read width from said first port.