Analog-to-digital converters employing cascaded phase-reversing switches

In an analog-to-digital (A/D) converter, responsive to 2N−1 different reference-values REF 1 to REF 2N−1 that divide the dynamic range of amplitude-values of an analog signal into 2N intervals, for converting the current amplitude-value of said analog signal S to binary values in accordance with a preselected N-Bit binary code, where N is a plural integer;

• the improvement wherein said A/D converter comprises:
• 2N−1 phase-reversing switches, each of which includes 3 input terminals and 1 output terminal;
• said phase-reversing switches being arranged between 1 and N columns, with at least one of said columns comprising a plurality of said phase-reversing switches, wherein the output terminal of each phase-reversing switch in said one column except the bottom phase-reversing switch is interconnected to the first input terminal of the immediately following phase-reversing switch in said one column, thereby interconnecting said plurality of said phase-reversing switches in said one column in cascade;
• first means for applying a given carrier frequency having a given relative phase φ to the first input terminal of that phase-reversing switch which is situated at the top of each of said 1 and N columns;
• second means for applying said analog signal S to the second input terminal of all of said 2N−1 phase-reversing switches;
• third means for applying a particular configuration of said 2N−1 different reference-values REF 1 to REF 2N−1 to the third input terminal of the respective 2N−1 phase-reversing switches that is determined by said preselected N-Bit binary code so that (1) whenever the amplitude value of the analog signal S reaches a value above the reference value REF applied to any given phase-reversing switch, that given phase-reversing switch will switch to reverse the relative phase at its output terminal from the relative phase at its first input terminal, and (2) consequently cause the switching of the relative phase at the output terminal of each phase-reversing switch that is ordinally situated in a column of phase-reversing switches below that given phase-reversing switch;
• whereby, as determined by the preselected binary code, the respective phases at the output terminals of a certain subset of N phase-reversing switches of the 2N−1 phase-reversing switches define the binary values of the preselected N-Bit binary code output from said A/D converter.