Inductor and capacitor formed of build-up vias
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsSung-Mao Wu, Chi-Tsung Chiu, Chih-Pin Hung
Life of this patent
Estimating the term…
Abstract
An inductor and capacitor implemented with build-up vias. The inductor and capacitor comprise a conductor plane, a dielectric layer, an inductor/capacitor inducing build-up via and a conductor layer. There is a conducting material in the inductor/capacitor inducing build-up via and a fist end thereof is in contact with the conductor plane. The length of the inductor inducing build-up via is larger than one fourth of a signal wavelength while the length of the conductor inducing build-up via is smaller than one fourth of a signal wavelength.
Claims6
An inductor comprised of a via, the inductor comprising:
- a conductor plane which is an unpatterned metal plane;
- a dielectric layer disposed on the conductor plane;
- an inductor inducing via disposed in the dielectric layer and filled with a conductive material, wherein the via does not fully penetrate through the dielectric layer;
- and
- a signal transmission layer, in contact with the conductive material in the inductor inducing via, wherein the signal transmission layer is a patterned circuit;
- wherein a length of the inductor inducing via is longer than one fourth of a signal wavelength.
A capacitor comprised of a via, the capacitor comprising:
- a conductor plane which is an unpatterned metal plane;
- a dielectric layer disposed on the conductor plane;
- a capacitor inducing via disposed in the dielectric layer and filled with a conductive material, wherein the via does not fully penetrate through the dielectric layer;
- and
- a signal transmission layer, in contact with the conductive material in the capacitor inducing via, wherein the signal transmission layer is a patterned circuit;
- wherein a length of the capacitor inducing via is smaller than one fourth of a signal wavelength.
Dependencies are inferred from the claim text.