Differential amplifier operable in wide range

A differential amplifier comprising:

• a differential amplifier circuit comprising first and second differential amplifier sections;
• wherein said first differential amplifier section comprises:
• a first differential pair of PMOS transistors which receives first and second input voltages, respectively;
• wherein said second differential amplifier section comprises:
• a second differential pair of NMOS transistors which receive said first and second input voltages, respectively;
• a bias circuit which only activates only one of said first and second differential amplifier sections in response to a control signal;
• and
• an output circuit which outputs an output signal from an output of said activated differential amplifier section,
• wherein said first differential amplifier section comprises:
• a first current mirror circuit whose input is connected with an output from one of said PMOS transistors of said first differential pair;
• and
• a second current mirror circuit whose input is connected with an output from the other of said PMOS transistors of said first differential pair,
• said second differential amplifier section comprises:
• a third current mirror circuit, one of whose outputs is connected with one of said NMOS transistors of said second differential pair;
• and
• a fourth current mirror circuit, one of whose outputs is connected with the other of said NMOS transistors of said second differential pair.

A differential amplifier comprising:

• a differential amplifier circuit comprising first and second differential amplifier sections;
• wherein said first differential amplifier section comprises:
• a first differential pair of PMOS transistors which receives first and second input voltages, respectively;
• wherein said second differential amplifier section comprises:
• a second differential pair of NMOS transistors which receive said first and second input voltages, respectively;
• a bias circuit which only activates only one of said first and second differential amplifier sections in response to a control signal;
• and
• an output circuit which outputs an output signal from an output of said activated differential amplifier section, and further comprising:
• a control signal generating circuit which generates said control signal based on said first and second input voltages.

A method of outputting an output signal from first and second input voltages in an differential amplifier circuit comprising first and second differential amplifier sections, wherein said first differential amplifier section comprises a first differential pair of PMOS transistors which respectively receives first and second input voltages, and wherein said second differential amplifier section comprises a second differential pair of NMOS transistors which respectively receives said first and second input voltages, said method comprising:

• activating only one of said first and second differential amplifier sections in response to a control signal;
• supplying first and second input voltages to said activated differential amplifier section;
• and
• outputting an output signal from an output of said activated differential amplifier section,
• wherein said activating comprises:
• (a) controlling a first constant current source for said first differential amplifier section to be tuned on and a second constant current source for said second differential amplifier section to be turned off when said first differential amplifier section is activated in response to said control signal;
• and
• (b) controlling said second constant current source to be turned on and said first constant current source to be turned off when said second differential amplifier section is activated in response to said control signal.

The method according to claim wherein said activating comprises:

• inverting said control signal;
• stopping an operation of said second constant current source in response to the inverted control signal, when said first differential amplifier section is activated in response to said control signal;
• and
• stopping an operation of said first constant current source in response to the inverted control signal, when said second differential amplifier section is activated in response to said control signal.

A method of outputting an output signal from first and second input voltages in an differential amplifier circuit comprising first and second differential amplifier sections, wherein said first differential amplifier section comprises a first differential pair of PMOS transistors which respectively receives first and second input voltages, and wherein said second differential amplifier section comprises a second differential pair of NMOS transistors which respectively receives said first and second input voltages, said method comprising:

• activating only one of said first and second differential amplifier sections in response to a control signal;
• supplying first and second input voltages to said activated differential amplifier section;
• outputting an output signal from an output of said activated differential amplifier section;
• and
• generating said control signal based on said first and second input voltages.

A differential amplifier comprising:

• a differential amplifier circuit comprising first and second differential amplifier sections;
• wherein said first differential amplifier section comprises:
• a first differential pair of PMOS transistors which receives first and second input voltages, respectively;
• wherein said second differential amplifier section comprises:
• a second differential pair of NMOS transistors which receive said first and second input voltages, respectively;
• a bias circuit which only activates only one of said first and second differential amplifier sections in response to a control signal;
• and
• an output circuit which outputs an output signal from an output of said activated differential amplifier section, and further comprising:
• a first input voltage terminal;
• and
• a second input voltage terminal, wherein,
• said first differential pair of PMOS transistors have gates respectively connected to the first and second input voltage terminals, and
• said second differential pair of NMOS transistors have gates respectively connected to the first and second input voltage terminals,
• said first and second differential amplifier sections comprise a first PMOS transistor and a first NMOS transistor connected as constant current sources respectively to the first and second differential pair transistors, respectively, and
• said bias circuit stops an operation of said first PMOS transistor when activating said second differential amplifier section, and stops an operation of said first NMOS transistor when activating said first differential amplifier section.

A differential amplifier comprising:

• a differential amplifier circuit comprising first and second differential amplifier sections;
• wherein said first differential amplifier section comprises:
• a first differential pair of PMOS transistors which receives first and second input voltages, respectively;
• wherein said second differential amplifier section comprises:
• a second differential pair of NMOS transistors which receive said first and second input voltages, respectively;
• a bias circuit which only activates only one of said first and second differential amplifier sections in response to a control signal;
• and
• an output circuit which outputs an output signal from an output of said activated differential amplifier section,
• wherein only said first differential amplifier section is activated when a voltage level of a predetermined signal is closer to a higher power supply voltage and only said second differential amplifier section is activated when the voltage level of the predetermined signal is closer to a lower power supply voltage.