Multi-mode digital bias control for enhancing power amplifier efficiency

A power amplifier including multi-mode digital bias control circuitry, the power amplifier capable of generating four different bias current levels in response to a combination of two control signals, the power amplifier comprising:

• a. a low power bias enable circuit, the low power bias enable circuit having a first input connected to a first reference voltage, and a second input connected to the first control signal;
• b. a high power bias enable circuit, the high power bias enable circuit having a first input connected to the first reference voltage, and a second input connected to the first control signal controls the first stage high power bias circuit and the second stage high power bias circuit;
• c. a bias current control circuit having an input connected to the second control signal;
• d. a low power bias circuit having a first input connected to output of the low power bias enable circuit, and a second input connected to a first output of the bias current control circuit;
• e. a first stage high power bias circuit having a first input connected to a first output of the high power bias enable circuit, and a second input connected to a second output of the bias current control circuit;
• and
• f. a second stage high power bias circuit having a first input connected to a second output of the high power bias enable circuit, and a second input connected to a third output of the bias current control circuit.

A power amplifier circuit having a first input node connected to a first reference voltage, a second input node connected to a ground, a first control input node connected to a first control signal, and a second control input node connected to a second control signal, the power amplifier circuit comprising:

• a. a complementary reference voltage generation circuit having a first input connected to a first reference voltage, and a second input connected to the first control signal;
• b. a bias current control circuit having an input connected to the first control signal;
• c. a low power bias circuit having a first input connected to a first output of the complementary reference voltage generation circuit, and a second input connected to a first output of the bias current control circuit;
• d. a first stage high power bias circuit having a first input connected to a second output of the complementary voltage reference generation circuit, and a second input connected to a second output of the bias current control circuit;
• e. a second stage high power bias circuit having a first input connected to the second output of the complementary voltage reference generation circuit, and a second input connected to a third output of the bias current control circuit;
• f. a high power input impedance matching circuit having a first node connected to an input signal and a second node connected to an output node of the first stage high power bias circuit, the high power input impedance matching circuit matching impedance between the input signal and an output signal of the first stage high power bias circuit;
• g. a low power input impedance matching circuit having a first node connected to an input signal and a second node connected to an output node of the low power bias circuit, the low power input impedance matching circuit matching impedance between the input signal and an output signal of the low power bias circuit;
• h. a first transistor having a base connected to the output of the first stage high power bias circuit, and an emitter connected to the ground;
• i. an inter-stage impedance matching circuit having a first node connected to a collector of the first transistor and a second node connected to an output of the second stage high power bias circuit, the inter-stage impedance matching circuit matching impedance between a signal at the collector of the first transistor and an output signal of the second stage high power bias circuit;
• j. a second transistor having a base connected to the output of the second stage high power bias circuit, and an emitter connected to the ground;
• k. a third transistor having a base connected to the output of the low power bias circuit, an emitter connected to the ground;
• i. a high power output impedance matching circuit having a first node connected to a collector of the second transistor and a second node connected to an output node, the high power output impedance matching circuit matching impedance between a signal at the collector of the second transistor and an output signal of the power amplifier circuit;
• m. a field effect transistor having source connected to the collector of the second transistor;
• n. a low power output impedance matching circuit having a first node connected to a collector of the third transistor and a second node connected to a drain of the field effect transistor;
• and
• o. a resistor having a first terminal connected to the gate of the field effect transistor, and a second terminal connected to the second input of the complementary reference voltage generation circuit.