Multi-threshold MOS circuits
AssigneeQUALCOMM Incorporated
InventorSumant Ramprasad
Life of this patent
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Abstract
A multi-threshold flip-flop includes a master latch, a slave latch, and at least one control switch. The master latch is composed of an input buffer formed with low threshold (LVT) transistors and a first latch circuit formed with LVT transistors. The slave latch is composed of a second latch circuit formed with high threshold (HVT) transistors and an output driver formed with LVT transistors. The at least one control switch enables or disables the LVT transistors and is implemented with at least one HVT transistor. The LVT and HVT transistors may be N-FETs and/or P-FETs. The multi-threshold flip-flop can operate at high speed, has low leakage current, and can save the logic state when disabled.
Claims17
An integrated circuit comprising at least one multi-threshold flip-flop, each multi-threshold flip-flop comprising:
- a master latch comprised of low threshold (LVT) transistors;
- a slave latch operative to sample and hold output data from the master latch for the multi-threshold flip-flop and comprised of first and second inverters formed with high threshold (HVT) transistors and coupled in a feedback configuration, and
- first and second pass switches formed with HVT transistors, the first pass switch being coupled to an input of the first inverter, and the second pass switch being coupled within the feedback configuration;
- and
- at least one control switch operative to enable or disable the LVT transistors.
An integrated circuit comprising at least one multi-threshold flip-flop, each multi-threshold flip-flop comprising:
- a master latch comprised of an input buffer formed with low threshold (LVT) transistors and a first latch circuit formed with LVT transistors;
- a slave latch operative to sample and hold output data from the master latch for the multi-threshold flip-flop and comprised of
- a second latch circuit comprising first and second inverters formed with high threshold (HVT) transistors and coupled in a feedback configuration,
- first and second pass switches formed with HVT transistors, the first pass switch being coupled to an input of the first inverter, and the second pass switch being coupled within the feedback configuration, and
- an output driver formed with LVT transistors;
- and
- at least one control switch operative to enable or disable the LVT transistors for the input buffer, the first latch circuit, and the output driver.
Dependencies are inferred from the claim text.