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US 7,248,087 B2Granted
Coarse delay tuner circuits with edge suppressors in delay locked loops
AssigneeNXP B.V.
InventorSri Navaneethakrishnan Easwaran
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Abstract
The invention discloses a delay locked loop which includes a coarse delay tuner circuit with edge suppressors suitable for use with delay locked loops (DLLs). The disclosed tuner circuit provides reduced lock time of the DLL circuit.
Claims14
A coarse delay tuner circuit for use with delay locked loops, said coarse delay tuner circuit comprising:
- an input node for receiving an input signal, wherein said input signal is a clock signal;
- a triggering circuit, said triggering circuit operationally coupled to said input node, wherein said triggering circuit conditions said input signal and to provides a first output signal in response to a threshold level being reached by said input signal;
- an edge suppressor circuit operationally coupled to said triggering circuit, wherein said edge suppressor circuit receives said first output signal, said edge suppressor circuit providinge a positive step signal as a second output signal, and wherein said edge suppressor circuit includes combinational means for logically combining said first output signal and said second output signal to produce a third output signal;
- and an output node for outputting said third output signal.
1 more element
A method for reducing lock time in a delay locked loop (DLL), said method comprising:
- providing an input node for receiving an input signal, wherein said input signal is a clock signal;
- providing a triggering circuit, said triggering circuit operationally coupled to said input node, wherein said triggering circuit conditions said input signal and provides a first output signal in response to a threshold level being reached by said input signal;
- providing an edge suppressor circuit operationally coupled to said triggering circuit, wherein said edge suppressor circuit receives said first output signal, said edge suppressor circuit providinge a positive step signal as a second output signal, and wherein said edge suppressor circuit includes combinational means for logically combining said first output signal and said second output signal to produce a third output signal;
- and providing an output node for outputting said third output signal.
1 more element
Dependencies are inferred from the claim text.