Leakage compensation for capacitors in loop filters

A circuit comprising:

• a first node that receives a first current;
• an integration capacitor having a first terminal coupled to the first node and a second terminal coupled to a reference voltage source, wherein the integration capacitor integrates the first current to produce an integrated voltage, and wherein a first leakage current correlated to the integrated voltage leaks from the integration capacitor;
• and
• a variable current source coupled to the first terminal, wherein the variable current source generates a compensation current;
• wherein the variable current source includes a second capacitor that leaks a second leakage current;
• and
• wherein the variable current source comprises a current mirror that generates the compensation current using the second leakage current.

A circuit comprising:

• a first node that receives a first current;
• an integration capacitor having a first terminal coupled to the first node and a second terminal coupled to a reference voltage source, wherein the integration capacitor integrates the first current to produce an integrated voltage, and wherein a first leakage current correlated to the integrated voltage leaks from the integration capacitor;
• a variable current source coupled to the first terminal, wherein the variable current source generates a compensation current and adds the compensation current to the integration capacitor;
• a charge pump that generates the first current in response to a least one of an up signal and a down signal;
• a phase and frequency detector coupled to the charge pump;
• and
• a variable delay line coupled between the integration capacitor and the phase and frequency detector.

A phase-locked loop comprising:

• a phase detector that receives a first clock signal and a feedback clock signal and that outputs phase error signals;
• a charge pump that generates a first current in response to the phase error signals;
• an integration capacitor that integrates the first current, wherein the integration capacitor leaks a leakage current;
• a leakage compensation circuit coupled to the integration capacitor, wherein the leakage compensation circuit generates a compensation current, wherein the integration capacitor integrates the first current, the leakage current, and the compensation current to produce an integration voltage;
• and
• an output circuit that produces the feedback clock signal in response to the integration voltage;
• wherein the leakage compensation circuit includes a compensation capacitor exhibiting a second leakage current.

A phase-locked loop comprising:

• a phase detector that receives a first clock signal and a feedback clock signal and that outputs phase error signals;
• a charge pump that generates a first current in response to the phase error signals;
• an integration capacitor that integrates the first current, wherein the integration capacitor leaks a leakage current;
• a leakage compensation circuit coupled to the integration capacitor, wherein the leakage compensation circuit generates a compensation current, wherein the integration capacitor integrates the first current, the leakage current, and the compensation current to produce an integration voltage;
• and
• an output circuit that produces the feedback clock signal in response to the integration voltage;
• wherein the leakage compensation circuit includes a compensation capacitor exhibiting a second leakage current;
• and
• wherein the leakage compensation circuit comprises a current mirror that generates the compensation current using the second leakage current.

A delay locked loop comprising:

• a phase detector that receives a first clock signal and a feedback clock signal and that outputs phase error signals;
• a charge pump that generates a first current in response to the phase error signals;
• a leakage compensation circuit that generates a compensation current;
• an integration capacitor that integrates the first current and the compensation current to produce an integration voltage, and wherein the integration capacitor leaks a leakage current;
• and
• an output circuit that generates the feedback clock signal in response to the integration voltage;
• wherein the output circuit comprises a variable delay line.

A circuit comprising:

• a loop filter having an input lead, a node and a capacitor, wherein a leakage current leaks from the node and through the capacitor;
• a voltage-controlled oscillator having an input lead coupled to the output lead of the loop filter, wherein the voltage-controlled oscillator outputs an output signal having a frequency that depends on a voltage on the node;
• and
• a leakage compensation circuit that supplies a compensation current onto the node, wherein the compensation current substantially equals the leakage current;
• wherein the leakage compensation circuit includes a second capacitor that leaks a second leakage current and a current mirror that generates the compensation current using the second leakage current.

A method comprising:

• generating a phase error signal indicative of a phase difference between a reference signal and a feedback signal;
• adding and subtracting charge onto and off of a node based on the phase error signal;
• accumulating the charge on the node using a first capacitor such that a voltage is present on the node, wherein the first capacitor leaks a leakage current;
• supplying a compensation current onto the node, wherein the compensation current substantially equals the leakage current;
• and
• controlling the frequency of the feedback signal based on the voltage on the node;
• wherein the supplying the compensation current employs a second capacitor.