Methods and systems for decreasing transmission timing variations

A system for decreasing transmission timing variations comprising:

• an N−1 first gate circuit for inputting associated data bits and generating a first output driving signal in response to a first clock signal;
• an N−1 output driver connected to a data channel and responsive to the first output driving signal;
• an NTH gate circuit for inputting the associated data bits and generating a second output driving signal in response to a second clock signal;
• and
• an NTH output driver connected to the data channel and responsive to the second output driving signal,
• wherein the NTH output driver is further responsive to a precharging control signal to precharge the data channel to a voltage level before a first data bit of the associated data bits is input.

A method for decreasing transmission timing variations comprising:

• inputting a precharging control signal;
• generating an output driving signal in response to the precharging control signal before a data bit is input;
• and
• precharging a data channel to a voltage level before the data bit is input using the output driving signal.

A method for decreasing transmission timing variations comprising:

• inputting associated data bits and generating an N−1 output driving signal in response to a first clock signal;
• inputting the associated data bits and generating an NTH output driving signal in response to a second clock signal;
• and
• precharging a data channel to a voltage level in response to a precharging control signal before a first data bit of the associated data bits is input.

In a system comprising a gate circuit for inputting a precharging control signal and for generating an output driving signal in response to the control signal before a data bit is input and an output driver connected to a data channel and responsive to the output driving signal for precharging the data channel to a voltage level before the data bit is input, a method for decreasing transmission timing variations comprising:

• inputting the precharging control signal;
• generating the output driving signal in response to the control signal before a data bit is input;
• and
• precharging the data channel to a voltage level before the data bit is input using the output driving signal.

In a system comprising an N−1 gate circuit for inputting associated data bits and generating a first output driving signal in response to a first clock signal, an N−1 output driver connected to a data channel and responsive to the first output driving signal, an Nth gate circuit for inputting associated data bits and generating a second output driving signal in response to a second clock signal and an NTH output driver connected to the data channel and responsive to the second output driving signal, wherein the second output driver is further responsive to a precharging control signal to precharge the data channel to a voltage level before a first data bit is input, a method for decreasing transmission timing variations comprising:

• inputting the associated data bits and generating the N−1 output driving signal in response to the first clock signal;
• inputting the associated data bits and generating the NTH output driving signal in response to the second clock signal;
• and
• precharging the data channel to the voltage level in response to the precharging control signal before the first data bit is input.