Sample-hold circuit
AssigneeFujitsu Limited
InventorsYasuhiro Nakasha, Tatsuya Hirose
Life of this patent
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Abstract
A sample-hold circuit, which reduces droop and feed through and is suitable for high-speed operation while maintaining a wider freedom of design parameters, comprising a preamplifier to which an input analog signal is applied, a core section which outputs a voltage corresponding to the variation of an output from the preamplifier during the sampling period and holds the voltage corresponding to the output from the preamplifier during the hold period initiated by a transition of a clock signal, and a current switching circuit which is connected to the output pin of the preamplifier and enables the current flowing into the first transistor within the preamplifier during the sampling period to flow into another second transistor to apply a constant potential as an input to the core section.
Claims3
A sample-hold circuit comprising a preamplifier to which an input analog signal is applied, comprising:
- a core section to which the amplified output of the input analog signal by said preamplifier is applied as an input, for outputting a voltage corresponding to the variation in the input analog signal, during the sampling period of the input analog signal, and for holding and outputting the value of the voltage corresponding to the amplified output at the time of the transition of a sample clock signal during the hold period;
- and
- a current switching circuit which is connected to the output pin of the preamplifier, for enabling a current flowing into a first transistor, comprised within the preamplifier during the sampling period, to flow into a second transistor to apply a constant potential as an input to the core section during the hold period,
- wherein said current switching circuit comprises:
- a third transistor which is connected to said first transistor and to the gate terminal of which said sample signal is applied;
- a fourth transistor which is connected to said second transistor and to the gate terminal of which a potential, which maintains said transistor ON in DC, is applied;
- and
- wherein the inverted signal of said sample clock signal is applied to the gate terminal of said second transistor.
A sample-hold circuit comprising a preamplifier to which an input analog signal applied, which comprises:
- a core section to which the amplified output of the input analog signal by the preamplifier is applied as input, during the sampling period of the input analog signal, the voltage corresponding to the variation of the input analog signal, and wherein the value of the voltage corresponding to the amplified output at the time of the transition of a sample clock signal is held and output during the hold period;
- a current switching circuit which is connected to the output terminal of the preamplifier, for enabling the current flowing into the first transistor provided within said preamplifier to flow into another second transistor to apply a constant potential as an input to the core section during the hold period;
- and
- said core section comprises third and fourth transistors which are connected in series and to each gate of which a sample clock signal is applied;
- a capacitance which is connected to one of the third and fourth transistors, for holding the value of the voltage corresponding to the output of the preamplifier at the time of the variation of the sample clock signal;
- and
- a diode which is connected to the capacitance in parallel and has a reverse polarity to that of the voltage held.
Dependencies are inferred from the claim text.