Differential buffer circuit with reduced output common mode variation

An integrated circuit including at least one differential buffer circuit, the at least one differential buffer circuit comprising:

• a current source;
• a current sink;
• a switching circuit connected to the current source at a first node and connected to the current sink at a second node, the switching circuit being operative to selectively control a direction of current flowing through differential outputs of the at least one buffer circuit in response to at least a first control signal applied to the switching circuit;
• a common mode detection circuit connected to the differential outputs of the at least one buffer circuit, the common mode detection circuit being operative to detect an output common mode voltage of the buffer circuit and to generate a second control signal representative of the output common mode voltage;
• and
• a common mode control circuit having a first terminal connected to the current source and a second terminal connected to the current sink, the common mode control circuit being operative to selectively control the output common mode voltage of the at least one buffer circuit as a function of the second control signal.

A bias circuit operative to generate at least first and second bias signals for biasing a differential buffer circuit, the bias circuit comprising:

• an “H” bridge circuit including:
• a current source;
• a current sink;
• and
• switching circuitry connected to the current source at a first node and connected to the current sink at a second node, the switching circuitry being operative to control a direction of current flowing through differential outputs of the “H” bridge circuit in response to at least a first control signal;
• a common mode detection circuit connected to the differential outputs of the “H” bridge circuit, the common mode detection circuit being operative to detect an output common mode voltage of the “H” bridge circuit and to generate a second control signal representative of the output common mode voltage;
• a common mode control circuit having a first terminal connected to the current source and a second terminal connected to the current sink, the common mode control circuit being operative to selectively control the output common mode voltage of the “H” bridge circuit as a function of the second control signal;
• a first operational amplifier including a first input connected to a first of the differential outputs of the “H” bridge circuit, a second input adapted to receive a first reference signal, and an output for generating the first bias signal;
• and
• a second operational amplifier including a first input connected to a second of the differential outputs of the “H” bridge circuit, a second input adapted to receive a second reference signal, and an output for generating the second bias signal.