Dual-voltage three-state buffer circuit with simplified tri-state level shifter

A dual-voltage three-state buffer circuit comprising:

• a tri-state logic control module operated under a low supply voltage and receiving a data input and a tri-state enable signal;
• a single level shifter for receiving one or more inputs from the tri-state logic control module and operating with an output control circuit for controlling a first and a second differential outputs of the level shifter;
• and
• a post driver circuit having a PMOS transistor and an NMOS transistor connected in series with the gates of PMOS and NMOS transistors driven by the first differential outputs of the level shifter respectively,
• wherein when the tri-state enable signal is not asserted, the data input is elevated to a high voltage output by the post driver circuit,
• wherein when the tri-state enable signal is asserted, the output control circuit operates with the level shifter to turn off the PMOS and NMOS transistors of the post driver circuit while isolating the level shifter from a high supply voltage in response to the inputs generated by the tri-state logic control module.

A three state level-shifter module adapted to control a post driver circuit having a PMOS transistor and an NMOS transistor connected in series between a high voltage and a low voltage, comprising:

• a single level shifter for receiving one or more inputs;
• and
• an output control circuit coupled with the single level shifter for controlling the single level shifter to output at least two differential outputs in response to the inputs,
• whereby the single level shifter is capable of controlling gates of the PMOS and NMOS transistors to provide three-state outputs and the output control circuit further includes at least one high voltage output switch coupled between a voltage supply and the single level shifter.