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US 7,248,075 B2Granted
Level shifter with low leakage current
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-Sun Min, Nam-Jong Kim
Life of this patent
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Abstract
A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow<VOlow, and wherein VOhigh>Vcc and VOlow<Vss.
Claims21
A voltage level shift circuit, comprising:
- a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow;
- and
- a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow<VOlow, and wherein VOhigh>Vcc and VOlow<Vss.
A circuit, comprising:
- a first voltage level shift circuit which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs an intermediate signal having voltage levels VIhigh and VIlow, where VIhigh>VIlow;
- and
- a second voltage level shift circuit which receives the intermediate signal from the first voltage level shift circuit, and which outputs an output signal having voltage levels VOhigh and VOlow, where VOhigh>Vcc, and Vss >VOlow,
- wherein at least one of (a) VIhigh>VOhigh, and (b) VIlow<VOlow.
1 more element
A circuit, comprising:
- a first voltage level shift circuit which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs an intermediate signal having voltage levels VIhigh and VIlow, where VIhigh>VIlow;
- and
- a second voltage level shift circuit which receives the intermediate signal from the first voltage level shift circuit, and which outputs an output signal having voltage levels VOhigh and VOlow, where V0high>VOlow,
- wherein the second voltage level shift circuit is an inverter, and
- wherein VIlow<VOlow, and wherein VIhigh=VOhigh=Vcc.
2 more elements
A circuit, comprising:
- a first voltage level shift circuit which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs an intermediate signal having voltage levels VIhigh and VIlow, where VIhigh>VIlow;and
- a second voltage level shift circuit which receives the intermediate signal from the first voltage level shift circuit, and which outputs an output signal having voltage levels VOhigh and VOlow, where VOhigh>VOlow,
- wherein the second voltage level shift circuit is an inverter which comprises:
- a first NMOS transistor having a gate which receives the first intermediate signal, and having a source connected to a first reference potential of VOlow;
- and
- a first PMOS transistor having a gate which receives the first intermediate signal, and having a source connected to a second reference potential of VOhigh, and a drain connected to the drain of the first NMOS transistor.
3 more elements
A circuit, comprising:
- a first voltage level shift circuit which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs an intermediate signal having voltage levels VIhigh and VIlow, where VIhigh>VIlow;
- and
- a second voltage level shift circuit which receives the intermediate signal from the first voltage level shift circuit, and which outputs an output signal having voltage levels VOhighand VOlow, where VOhigh>VOlow,
- wherein at least one of (a) VIhigh>VOhigh, and (b) VIlow<VOlow, and
- wherein the second voltage level shift circuit is a word line decoder for a memory circuit.
2 more elements
A method of level shifting an input signal, comprising:
- receiving at a first stage of a level shift circuit an input signal having voltage levels Vcc and Vss, where Vcc>Vss;
- outputting from the first stage complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow;
- and
- receiving at a second stage of the level shift circuit the first and second intermediate signals;
- and
- outputting from the second stage complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow<VOlow, and wherein VOhigh>Vcc and VOlow<Vss.
3 more elements
A method of generating a word line for a memory circuit, comprising:
- receiving at a level shift circuit an input signal having voltage levels Vcc and Vss, where Vcc>Vss;
- outputting from the level shift circuit a first intermediate signal, wherein the first intermediate signal has voltage levels Vlhigh and VIlow, where VIhigh>VIlow;
- receiving at a word line decoder the first intermediate signal;
- outputting from the word line decoder a second intermediate signal, wherein the second intermediate signal has voltage levels VIhigh and VOlow;
- receiving at a word line driver the second intermediate signal;
- outputting from the word line driver a word line signal, wherein the word line signal has voltage levels VOhigh and VOlow,
- where VOhigh>VOlow, where VIhigh>VOhigh, where VIlow<VOlow, and where VOhigh>Vcc and VOlow<Vss.
4 more elements
Dependencies are inferred from the claim text.