Configurable logic element with expander structures

A method for enhancing the flexibility of a programmable logic circuit of a programmable logic device (PLD), the programmable logic circuit comprising an expander structure and a lookup table structure (LUT), the method comprising the steps of:

• providing a multiplexer for receiving a first input from an output of the expander structure and a second input from an output of the LUT and selecting either the output of the expander structure or the output of the LUT as an unregistered output;
• providing simultaneous access to the output of the expander structure and the unregistered output as separate outputs of the programmable logic circuit;
• and
• providing a flip-flop connected to the unregistered output of the multiplexer for providing a registered output.

A programmable logic block, comprising:

• a logic array operable to generate a first signal;
• a first expander circuit coupled to the logic array and operable to receive a second signal from a second expander circuit of another programmable logic block and to generate a third signal from the first and second signals;
• a multiplexer operable to receive the first and third signals and to pass a selected one of the first and third signal;
• and
• a flip-flop that is operable to receive the selected signal passed by the multiplexer.

An electronic system, comprising:

• an integrated circuit, comprising,
• a first programmable logic block having a first expander circuit operable to generate a first signal, and
• a second programmable logic block comprising,
• a logic array operable to generate a second signal,
• a second expander circuit coupled to the first programmable logic block and to the logic array and operable to generate a third signal from the first and second signals,
• a multiplexer operable to receive the second and third signals and to pass a selected one of the second and third signals;
• and
• a flip-flop that is operable to receive the selected signal passed by the multiplexer.

A method, comprising:

• generating a first signal with a first expander circuit of a first programmable logic block;
• generating a second signal with a logic array of a second programmable logic block;
• generating from the first and second signals a third signal with a second expander circuit of the second programmable logic block;
• selectively passing one of the second and third signals to an output node of the second programmable logic block;
• and
• registering the passed signal prior to providing the passed signal to the output node of the second programmable logic block.