On-chip analysis and computation of transition behavior of embedded nets in integrated circuits

A method for measuring a transient response of an embedded net in an integrated circuit, comprising the steps of:

• generating at least one of:
• a reference voltage and a reference current;
• generating programmable step delays;
• comparing an output from a circuit under test with at least one of:
• the reference voltage and the reference current;
• latching an output of the comparison;
• and
• coordinating the reference generation, step delay generation, comparison, and latching steps to provide a transient response measurement.

A system, comprising:

• an integrated circuit comprising one or more nodes;
• and
• a testing apparatus comprising:
• a reference step generator capable of providing at least one of:
• programmable reference voltages and programmable reference currents;
• a step delay generator capable of providing programmable delays;
• a comparator capable of receiving an output of the reference step generator on a first input, an output from one of the nodes at a second input, and a latch enable signal from the step delay generator, the comparator also capable of providing a latched digital output in response to a comparison;
• and
• a controller capable of coordinating operation of the reference step generator, the step delay generator, and the comparator to provide a transient response measurement.