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US 7,247,935 B2Granted
Semiconductor device
AssigneeNEC Electronics Corporation
InventorMasaya Kawano
Life of this patent
Estimating the term…
Abstract
A semiconductor device, which is constituted in such a way that a pad portion of a logic chip is connected to an element region of a semiconductor chip with a bump bonding, is capable of achieving high speed operability of the elements, because delay of transmission of an electrical signal is suppressed a logic chip is directly connected to a DRAM, therefore, it is possible to suppress an increase of load capacitance caused by interconnects, and securing a wide bus width by a multiple pin connection. As a result, it becomes possible to enhance performance of the semiconductor device upon suppressing delay of information transmission from the logic chip to the DRAM.
Claims15
A semiconductor device comprising:
- a first semiconductor chip with a first pad on a main face of said first semiconductor chip;
- a second semiconductor chip;
- said second semiconductor chip having a semiconductor substrate with a substrate front surface and a substrate rear surface;
- a multi-level interconnect layer provided on a front surface of said semiconductor substrate;
- a through electrode, which penetrates said semiconductor substrate completely from the substrate front surface to the substrate rear surface, being connected to a conductive component provided within said multi-level interconnect layer;
- and
- a second pad mounted on a top of said multi-level interconnect layer, wherein,
- said first semiconductor chip and said second semiconductor chip are flip-chip connected with each other via said first pad and said second pad,
- said second semiconductor chip further comprises a logic circuit and a multilayer converter circuit,
- the logic circuit and the plural interconnect layers occupy a first area of the substrate front surface, and
- the multilayer converter circuit occupies a second area, distinct from and coplanar with the first area, of the substrate front surface,
- the second area being in vertical registration with the through electrodes, and
- at least one layer of the multilayer converter circuit is connected to a corresponding interconnect layer, and at least one layer of the multilayer converter circuit is connected to ao corresponding through electrode.
10 more elements
A semiconductor device comprising:
- a first semiconductor chip (140) with a first bump (142) located on and extending beyond a main face of said first semiconductor chip;
- and
- a second semiconductor chip (200) having
- i) a semiconductor substrate (102) with a substrate front surface and a substrate rear surface,
- ii) a logic circuit (116) having a logic circuit element layer (149) formed on the front surface of said semiconductor substrate and multi-level logic circuit interconnect layers (144, 146, 148) provided on the front surface of said semiconductor substrate and over said logic circuit element layer,
- iii) a converter circuit (103) having converter circuit element layer (113) formed on the front surface of said semiconductor substrate, and multi-level converter interconnect layers (104, 106, 108) provided on the front surface of said semiconductor substrate and over said converter circuit element layer,
- iv) a plurality of through electrodes penetrating said semiconductor substrate completely from the substrate front surface to the substrate rear surface, and
- v) a second bump (120) mounted on and extending beyond a top of said multi-level logic circuit interconnect layers, wherein
- said first semiconductor chip and said second semiconductor chip are flip-chip connected with each other via said first bump and said second bump, and
- the logic circuit element layer and the multi-level logic circuit interconnect layers occupy a first area of the substrate front surface, and the converter circuit element layer and the multi-level converter interconnect layers occupy a second area of the substrate front surface,
- the second area being distinct from the first area and in vertical registration with the through electrodes, and
- at least one layer of the converter circuit element layer and the multi-level converter interconnect layers is connected to a corresponding multi-level logic circuit interconnect layer, and at least one layer of the converter circuit element layer and the multi-level converter interconnect layers is connected to a corresponding through electrode.
9 more elements
A semiconductor device comprising:
- a first semiconductor chip with a first bump located on and extending beyond a main face of said first semiconductor chip;
- and
- a second semiconductor chip having
- i) a semiconductor substrate with a substrate front surface and a substrate rear surface,
- ii) a logic circuit having a logic circuit element layer formed on the front surface of said semiconductor substrate and multi-level logic circuit interconnect layers provided on the front surface of said semiconductor substrate and over said logic circuit element layer,
- iii) a buffer circuit (111) having a buffer circuit element layer (115) formed on the front surface of said semiconductor substrate, and multi-level buffer interconnect layers (105, 107, 109) provided on the front surface of said semiconductor substrate and over said buffer circuit element layer, and
- iv) a plurality of through electrodes penetrating said semiconductor substrate completely from the substrate front surface to the substrate rear surface;
- and
- v) a second bump mounted on and extending beyond a top of said multi-level logic circuit interconnect layers, wherein
- said first semiconductor chip and said second semiconductor chip are flip-chip connected with each other via said first bump and said second bump, and
- the logic circuit element layer and the multi-level logic circuit interconnect layers occupy a first area of the substrate front surface, and the buffer circuit element layer and the multi-level buffer interconnect layers occupy a second area of the substrate front surface,
- the second area being distinct from the first area and in vertical registration with the through electrodes, and
- at least one layer of the buffer circuit element layer and the multi-level buffer interconnect layers is connected to a corresponding multi-level logic circuit interconnect layer, and at least one layer of the buffer circuit element layer and the multi-level buffer interconnect layers is connected to a corresponding through electrode.
10 more elements
A semiconductor device comprising:
- a first semiconductor chip with a first bump located on and extending beyond a main face of said first semiconductor chip;
- and
- a second semiconductor chip having
- i) a semiconductor substrate with a substrate front surface and a substrate rear surface,
- ii) a circuit having a circuit element layer and formed on the front surface of said semiconductor substrate and multi-level circuit interconnect layers provided on the front surface of said semiconductor substrate and over said circuit element layer, wherein said circuit does not have a converter circuit,
- iii) a converter circuit having converter circuit element layer formed on the front surface of said semiconductor substrate, and multi-level converter interconnect layers provided on the front surface of said semiconductor substrate and over said converter circuit element layer,
- iv) a plurality of through electrodes penetrating said semiconductor substrate completely from the substrate front surface to the substrate rear surface, and
- v) a second bump mounted on and extending beyond a top of said multi-level logic circuit interconnect layers, wherein
- said first semiconductor chip and said second semiconductor chip are flip-chip connected with each other via said first bump and said second bump, and
- the circuit element layer and the multi-level circuit interconnect layers occupy a first area of the substrate front surface, and the converter circuit element layer and the multi-level converter interconnect layers occupy a second area of the substrate front surface,
- the second area being distinct from the first area and in vertical registration with the through electrodes, and
- at least one layer of the converter circuit element layer and the multi-level converter interconnect layers is connected to a corresponding multi-level circuit interconnect layer, and at least one layer of the converter circuit element layer and the multi-level converter interconnect layers is connected to a corresponding through electrode.
9 more elements
A semiconductor device comprising:
- a first semiconductor chip with a first bump located on and extending beyond a main face of said first semiconductor chip;
- and
- a second semiconductor chip having
- i) a semiconductor substrate with a substrate front surface and a substrate rear surface,
- ii) a circuit having a circuit element layer formed on the front surface of said semiconductor substrate and multi-level logic circuit interconnect layers provided on the front surface of said semiconductor substrate and over said circuit element layer, wherein said circuit does not have a buffer circuit,
- iii) a buffer circuit having a buffer circuit element layer formed on the front surface of said semiconductor substrate, and multi-level buffer interconnect layers provided on the front surface of said semiconductor substrate and over said buffer circuit element layer, and
- iv) a plurality of through electrodes penetrating said semiconductor substrate completely from the substrate front surface to the substrate rear surface;
- and
- v) a second bump mounted on and extending beyond a top of said multi-level logic circuit interconnect layers, wherein
- said first semiconductor chip and said second semiconductor chip are flip-chip connected with each other via said first bump and said second bump, and
- the circuit element layer and the multi-level circuit interconnect layers occupy a first area of the substrate front surface, and the buffer circuit element layer and the multi-level buffer interconnect layers occupy a second area of the substrate front surface,
- the second area being distinct from the first area and in vertical registration with the through electrodes, and
- at least one layer of the buffer circuit element layer and the multi-level buffer interconnect layers is connected to a corresponding multi-level logic circuit interconnect layer, and at least one layer of the buffer circuit element layer and the multi-level buffer interconnect layers is connected to a corresponding through electrode.
10 more elements
Dependencies are inferred from the claim text.