Chip package with capacitor
AssigneeMegica Corporation
InventorsMou-Shiung Lin, Bryan Peng
Life of this patent
Estimating the term…
Abstract
A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.
Claims56
A chip package comprising:
- a circuit substrate;
- a first chip over said circuit substrate;
- a second chip over said circuit substrate;
- a first bump under said circuit substrate;
- a second bump under said circuit substrate;
- a third bump between said first chip and said circuit substrate, wherein said third bump has a height less than that of said first bump;
- and
- a first passive device under said circuit substrate, wherein said first passive device is between said first and second bumps.
A chip package comprising:
- a circuit substrate;
- a first chip over said circuit substrate;
- a first bump under said circuit substrate;
- a second bump connecting said first chip and said circuit substrate, wherein said second bump has a height less than that of said first bump;
- a first passive device over said circuit substrate;
- a second passive device under said circuit substrate.
A chip package comprising:
- a circuit substrate comprising a via connector extending in a vertical direction and a ground plane spreading in a horizontal level and contacting said via connector;
- a first chip joined with said circuit substrate;
- a second chip joined with said circuit substrate;
- a capacitor connected to said circuit substrate;
- and
- a connecting portion over said via connector and over said circuit substrate, wherein said connecting portion connects said via connector and said capacitor.
A chip package comprising:
- a circuit substrate comprising a via connector extending in a vertical direction and a ground plane spreading in a horizontal level and contacting said via connector;
- a first bump under said circuit substrate, wherein said first bump comprises solder;
- a first chip over said circuit substrate;
- a capacitor over said circuit substrate;
- and
- a connecting portion over said via connector, wherein said connecting portion connects said via connector and said capacitor.
A chip package comprising:
- a circuit substrate consisting of multiple circuit layers arranged in parallel, the topmost one of said multiple circuit layers comprising a trace, a first contact and a second contact, said trace said first and second contacts, wherein said trace is at the same horizontal level as said first and second contacts are;
- a first chip over said circuit substrate;
- a first bump between said first chip and said first contact, wherein said first bump is in contact with said first contact;
- and
- a passive device over said circuit substrate, wherein said passive device is connected to said second contact.
A chip package comprising:
- a circuit substrate;
- a first chip over said circuit substrate;
- a second chip over said circuit substrate;
- and
- a passive device over said circuit substrate, wherein said passive device is between said first and second chips, and wherein said circuit substrate comprises a portion connecting said first and second chips and said passive device.
Dependencies are inferred from the claim text.